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Scalling to 22 nm Process




Looking Forward to 22 nm

As it does with every technology node, the industry will evaluate some fairly radical changes at 22 nm.

Laura Peters, Editor-in-Chief -- Semiconductor International, 1/1/2009

To get to the 22 nm node, engineers will have to make a lot of critical decisions — such as whether to change from a planar CMOS structure to multigate; whether to use alternative channel materials; or whether to switch from tungsten to copper plugs.

Each of these represents a rather drastic and fairly risky change. As the industry has witnessed in the past, such critical changes will not take place unless the performance gains cannot be managed by simpler, less risky means (Table 1). This article will explore the various tools in the 22 nm toolbox that could or might be used to bring the 22 nm node to fruition.

No more happy scaling

At the 22 nm node, the "happy" era of scaling, when dimensional shrinks led almost directly to performance gains, has long been over and the industry is clearly in the era of equivalent scaling. Even so, downscaling will continue to 22 nm and beyond. Interestingly, the 22 nm node will just happen to coincide with ~22 nm physical gate length in high-performance logic devices — something that hasn't occurred for several cycles. A 22 nm device is expected to be introduced by 2011 or 2012. Likewise, the 16 nm technology node will have ~16 nm gates for high-performance devices. More accurately, the "node" designation refers to the DRAM metal 1 half-pitch or the flash poly gate uncontacted half-pitch, which, according to the International Technology Roadmap for Semiconductors (ITRS), will both follow three-year cycles after 2009. NAND flash device makers have been the most aggressive in scaling pitch, whereas DRAM makers drive aggressive high-k material adoption.

22 nm toolbox


1. To manage 90 nm gate pitch, significant shifts in gate length, spacer width and contact size were required. (Source: IBM)1
There is very little published data on 22 nm devices; even experimental devices. However, analysis of one recent 22 nm-scale device gives insight into the tools in the 22 nm toolbox. At the recent International Electron Devices Meeting (IEDM), IBM researcher B.S. Haran and colleagues at IBM, AMD and Freescale demonstrated proof-of-concept on a 25 nm gate length device, which required a significant shrink in gate dimension, spacer thickness (18 nm) and contact size (~26 nm) vs. the previous generation.1 The group chose to use quadrupole illumination with double patterning (double exposure/double etch) and pattern transfer from a trilayer resist to a hard mask to pattern these dimensions, including a gate pitch of only 90 nm (Fig. 1). Other key enablers of the ultrasmall (0.1 μm2) SRAM cell include band edge high-k/metal gate stacks, novel co-implants, a thin composite oxide/nitride deposition and etch for the spacers, advanced activation techniques, thin nickel silicide and copper contacts with a ruthenium liner. Low thermal budget had to be maintained to minimize effective diffusion of the source/drain and extension implants.

Haran said that the contact module was the most challenging to develop. To identify the optimum process flow, multiple iterations of device design experiments were performed in conjunction with TCAD simulations.

Litho capability

A primary tool in the toolbox must be lithography capable of patterning 22 nm features. 193 nm litho with water immersion (NA=1.35) and single patterning allows k1 scaling to 0.3 and resolution of 32 nm. With double patterning (Table 2) and resolution enhancement techniques, k1 is 0.15 and ~22 nm features can be patterned, but the CD control and overlay depend on the method. Double patterning suffers from increased costs, increased defectivity and smaller overlay budget (from 33%CD to 10%CD) relative to single patterning.

The spacer-defined patterning (self-aligned) approach has gained the most attention, but it is limited to regular structures (i.e., memory) and involves many deposition and etching steps. One way to minimize the cost of ownership (CoO) is by using higher-throughput scanners and resist freezing, which eliminates the intermediate etch step.

Beyond double patterning, all bets are on extreme ultraviolet (EUV) lithography to be available in the 2012 timeframe for 22 nm. The key challenge with EUV performance is simultaneously achieving feature resolution, line-edge roughness (LER) and exposure sensitivity. To date, research house IMEC (Leuven, Belgium) has demonstrated the ability to resolve 35 nm flash patterns with acceptable CD uniformity (1.5 nm 3σ). However, progress is still required at the EUV system level, especially with improved source power, from a current level of 120 W to 170 W and eventually 250 W (intermediate focus). IMEC is currently using a discharge-produced plasma (DPP) source, but the jury is still out on whether a DPP or laser-produced plasma (LPP) may ultimately prove to be the most production-worthy. Beyond the EUV system, producing and maintaining defect-free masks in the fab will be critical and photoresist performance must be improved as well.

Transistor changes

The most important levers in boosting the performance of CMOSFETs at the 45 and 32 nm nodes have been strain engineering and the move to high-k/metal gates from oxide/poly gates. Both of these approaches are considered relatively low risk relative to a move to multigate FETs, incorporating alternative channel materials or moving to metallic source and drain regions.

Strain this, stress that

At the 22 nm node, strain engineering techniques that scale with pitch will be used to enhance nMOS and pMOS transistor performance. To a great extent, stress techniques have proven to be additive. In addition to the tensile and compressive stress liners and stress memorization methods, embedded SiGe in the pMOS source/drain (S/D) regions have proven production-worthy for the 45 and 32 nm nodes.

Embedded carbon-doped silicon (~1–2% substitutional C) in the nMOS has been difficult to stabilize and keep the carbon dispersed in the silicon lattice through the various annealing steps. In addition, the benefits of eSiC have been elusive. However, recent work from researchers at AMD (Hopewell Junction, N.Y.), IBM and Freescale demonstrated >9% drive current enhancement and 25% mobility enhancement with eSiC and tensile liner over the 45 nm device with tensile liner and stress memorization.2 Also, the eSiC stressor demonstrated better scalability than the tensile liner/stress memorization combination for poly pitches from 380 to 190 nm. This work was in contrast to previous reports that showed degraded drive currents in short channel devices with thin oxides and embedded Si:C. The group determined that obtaining the desired electrical connections between the in situ phosphorus-doped SiC epi to nMOSFET extensions has to do with low extension doping concentrations, so eSiC is more difficult to enable with ultrashallow junctions and extremely high extension dopant concentrations. Extension resistance must be carefully optimized.

One method of improving pMOSFET drive currents involves switching substrates from the long-used (100) silicon to (110) silicon. Intel recently reported a 15% improvement in drive current of the pMOS transistor, while taking only a ~6% degradation in Ion of the nMOS transistor at 45 nm design rules.3 Importantly, the nMOS transistor is expected to degrade less with scaling. However, the benefits of making a transition to the new substrate are only beginning to be explored.

Scientists need to determine exactly how scalable the technology is. In addition, practical matters must be considered. For instance, there should be more silicon waste associated with growing the (110) silicon ingot and slicing the wafers, so there may be cost considerations.

Finally, alternative channel materials such as germanium and III–V materials are being considered for mobility improvements. At least for the 22 nm node, this option would be too disruptive, complicated and expensive to implement.

High-k/metal gate


2. SRAM threshold voltage mismatch increases as device dimensions shrink. By adopting high-k/metal gate, the trend is reversed. (Source: Intel)
Introduced first by Intel at the 45 nm node and expected to be put into production by other companies at the 32 nm node, high-k allows significantly reduced gate leakage and continued scaling of effective oxide thickness (EOT). In combination with metal gates, polysilicon depletion is eliminated and the threshold voltage pinning problem is eliminated. Because of increased gate control to the channel from inversion layer thickness scaling, the move to high-k/metal gate transistors also allowed a reversal of the threshold voltage mismatch trend for the first time (Fig. 2). As a result, ~50% SRAM scaling is realized for 32 nm low-power technology with improved cell read current at lower standby leakage than 45 nm.4 The move to high-k/metal gates at the 45 nm node enabled 0.7× EOT scaling while reducing gate leakage by >25× for the nMOS and 1000× for pMOS.5

High-k/metal gates can be manufactured using a gate-first or damascene-based replacement gate approach. Most gate-first approaches are using a hafnium oxide based dielectric with TiN gate. The nFET workfunction modulation and Vt control is accomplished by a thin lanthanum oxide layer cap on the high-k layer. For the pFET, a thin aluminum oxide is sputtered onto the oxide to shift the device's Vt independent of the metal workfunction. In fact, recent studies show that the lanthanum dopant diffuses into the high-k/SiO2 interface and forms a dipole, which shifts the band offset and therefore the effective workfunction of the electrode.6

The change to high-k/metal gates did more than improve device performance. It changed the dynamics of threshold voltage variability. In oxide/poly transistors, random dopant fluctuations in the channel are believed to be the major cause of local threshold voltage variability in MOSFETs. Threshold voltage mismatch between two nearby transistors is a function of device area and gate dielectric thickness.

Researchers Olivier Weber and colleagues at CEA-Leti Minatec (Grenoble, France), Soitec and STMicroelectronics recently explored the contributors to threshold voltage variability of a high-k/metal gate stack device on a fully depleted SOI substrate. The group showed that dipoles in the high-k gate dielectric and/or workfunction fluctuations in the TiN gate are the major contributors to local Vt variability in the 25 nm FDSOI devices.7 Scaling of the silicon thickness had a negligible impact on Vt variability down to a silicon thickness of 7 nm.

Another way that threshold voltage variation can be reduced is by making the transition to a double-gate finFET device, either on an SOI or bulk silicon substrate. In particular for the SRAM device, where superior short channel effect (SCE) immunity can be obtained and channel dopant concentration is lower or non-existent, the finFET is a promising candidate structure. Interestingly, early work on finFETs was primarily performed on SOI substrates, which has shifted in recent years to work on bulk silicon.

The challenge, even if finFETs prove to be the superior architecture for SRAMs, is their co-integration with planar CMOS. To be feasible, the two process flows must share many common steps to avoid an uneconomical number of mask steps. Another interesting finding is that stress techniques have not been as effective at improving the mobility of charge carriers, and therefore the drive current, in multigate FETs.3

Interconnect scaling

To accommodate a 22 nm process, tungsten contacts need a scaled titanium nitride liner (deposited by ALD) and scaled tungsten ALD seed process, followed by W-CVD fill.8 Although logic devices may have high-aspect-ratio contacts, it is the stacked capacitor DRAMs that push the envelope for this process (AR~20).

The extension of the copper/barrier structure to 22 nm will not be as simple. The increasing resistance of copper at reduced cross-section, as well as grain boundary and surface scattering effects will mean that the traditional Ta/TaN/copper structure will likely not scale to the 22 nm node with its 60 nm metal 1.

With ionized PVD processes, the TaN barriers can be scaled to ~8 nm. ALD TaN does not adhere well to copper. Ruthenium is considered a good adhesion layer, though it is a poor copper barrier — so a TaN or TiN barrier would still be required. If it is properly deposited, copper can be directly plated on ruthenium. There are many development efforts aimed at bringing a Ru/Cu-based interconnect into production. Both silver (Cu-Ag) and manganese (Cu-Mn) alloys are being considered for improved interconnect reliability. Upon annealing manganese, a self-forming MnO barrier with superior reliability forms. Both alloys have a small, negative impact on resistivity.

To reduce interline capacitance, low-k materials with k in the 2.2–2.5 range will be integrated at the 22 nm node. Another alternative is air gap approaches, most of which involve thermal decomposition of a porogen material. Integration with the assembly and packaging processes is critical with all these processes.

  1. B.S. Haran, "22 nm Technology Compatible Fully Functional 0.1 μm2 6T-SRAM Cell," 2008 IEDM Proc., p. 625.
  2. B. Yang et al., "High-Performance nMOSFET With In-Situ Phosphorus-Doped Embedded (ISPD eSi:C) Source-Drain Stressor," 2008 IEDM Proc., p. 51.
  3. L. Peters, "Multigate FETs: A Risky Proposition,", Dec. 15, 2008.
  4. H.S. Yang, "Scaling of 32 nm Low Power SRAM With High-k Metal Gate," 2008 IEDM Proc., p. 233.
  5. K. Mistry, "A 45 nm Logic Technology With High-k + Metal Gate Transistors, Strained Silicon 9 Cu Interconnect Layers, 193 nm Dry Patterning and 100% Pb-Free Packaging," 2007 IEDM Proc., p. 247.
  6. C.Y. Kang, "The Impact of La-Doping on the Reliability of Low Vt High-k/Metal Gate nMOSFET Under Various Gate Stress Conditions," 2008 IEDM Proc., p. 115.
  7. O. Weber et al., "High Immunity to Threshold Voltage Variability in Undoped Ultra-Thin FDSOI MOSFETs and its Physical Understanding," 2008 IEDM Proc., p. 245.
  8. F. Huang, A. Chandrashekar and M. Danek, "Resistivity Reduction Enables Tungsten Scaling," Semiconductor International, November 2008, p. 24.