65 nm Process Technology for 3G mobile Applications at Qualcomm and TI

Given the significant market size for the cell phone industry and the different types of products available, it's not surprising that Qualcomm and Texas Instruments offer a number of different baseband solutions. Their semiconductor devices have been advancing to accommodate the wide variety of systems, taking into account different size, power consumption and functionality restrictions.

For a full archive of articles and related On-Demand seminars, click here

Qualcomm's road map has four platforms of baseband devices, including value, multimedia, enhanced multimedia and convergence. Each accommodates different levels of cell phone offerings and the different networks on which they operate. Recent Qualcomm devices analyzed by Semiconductor Insights (SI), such as the MSM6260, fall within the multimedia platform family. These devices are interesting due to the process technology migration and lithography shrink that have been implemented to increase functionality without drastically increasing the die size or power consumption.

Things have been quite interesting for Qualcomm recently. The Nokia-Qualcomm licensing agreement expired on April 9, and there is no new agreement. This has some serious implications for Nokia, as it could prevent it from selling its third-generation (3G) handsets that use Qualcomm parts, of which there are many. Nokia offered Qualcomm $20 million to be allowed to continue using the patents, claiming that the sum was a "fair and reasonable" amount. Qualcomm disagreed, and subsequently filed a demand for arbitration by the American Arbitration Association. It will be of great interest to see how this issue is resolved. Considering their strong positions, both Qualcomm and Nokia have much to gain, as well as lose, from working together.

The Qualcomm mobile station modem (MSM) 6260 is fabricated using Taiwan Semiconductor Manufacturing Co.'s 65-nanometer process and is designed for mainstream 3G mobile applications that operate on wideband-CDMA (UMTS) and GSM/GPRS/Edge networks. The MSM6260 was one of the first devices to be fabricated in TSMC's 65-nm technology that SI has seen. As a multimedia platform, the MSM6260 allows for shortened design cycles and reduced development costs. By incorporating a common chip set platform that is optimized for 3G networks used throughout the world, it allows handset makers to offer multiple device designs. It is also RF- and pin-compatible with other chip set solutions being offered by Qualcomm, such as the MSM6245 and the MSM6255A.

From 90 nm to 65 nm
A process predecessor to the MSM6260, the MSM6250A was fabricated using TSMC's 90-nm CMOS process technology. In late 2004, TSMC reported a number of features and options for its 90-nm process. These have, in part, evolved through the closer working relationships foundries have developed with their customers to better accommodate design-specific requirements. This cooperation is improving from generation to generation and will likely continue as more integrated device manufacturers consider the foundry option for their leading-edge designs.

TSMC's triple-gate process is an example of that trend. This option provides for multiple-gate dielectric thicknesses, helping to remove design restrictions caused by core/IO combination requirements. In addition, low-power processes for mobile applications or high-performance processes for speed-sensitive applications (such as gaming applications) are available.

TSMC introduced some technology changes in scaling its 90 nm to 65 nm. SI's analysis of the MSM6250A revealed that the device was produced in what appears to be the 90-nm low-power process, utilizing 80-nm minimum gate length, a dual gate process coupled with conventional Cobalt silicide and a less aggressive six-layer copper using top Al interconnect.

TSMC introduced its 65-nm process in early 2006. It claims to have almost doubled the density of its 90-nm process, boasting a 50 percent increase in speed and 20 percent standby power reduction. The company appears to have improved mobility by introducing a 3-D process—induced strain associated with shallow trench isolation, silicide and cap layer. With the introduction of nickel silicide for ultrashallow junction formation, these changes have helped TSMC to attain the speed and power requirements needed by its customers. In addition, there are some increased benefits to the manufacturability of the process, such as the contact etch stop performance of the Ni-silicide that is required for ultrashallow junctions.

TSMC is now on its third generation of low-k dielectric integration and fourth generation of Cu interconnect integration. Qualcomm's MSM6260 was manufactured using a six-level Cu process, also using top Al interconnect (similar to the 90-nm technology used for the MSM6250A). Although this may have allowed Qualcomm a straight shrink with minimal redesign for some of its reused functional blocks, the die size of the MSM6260 is similar to that of the MSM6250A. This indicates a significantly higher level of functionality and more features than those used for the MSM6250A.

The scaling technology choices made by TSMC have allowed it to increase the number of transistors per unit area, while delivering on the most important feature to mobile applications designers such as Qualcomm: power. Although the sidewall spacers have been slightly modified to help scale the source and drain junction in the channel regions and Ni-silicidation of the poly has replaced Co-silicide, the 90-nm and 65-nm transistor structures look similar. No paradigm shift in the process technology appears to have been introduced beyond typical evolution of techniques required for traditional scaling.

Most notable in the 6260 design is the SRAM cell size reduction of almost 60 percent. This is in part achieved by the more aggressive lithography as well as design rules allowing closer contact-gate spacing.

Furthermore, decreasing inter-metal dielectric layer thickness has helped scale aspect ratios of the metal lines. This can help maintain liner thickness and step coverage in the lower sidewall regions of the vias and achieve the highest-aspect-ratio metal lines.

With a gate thickness of approximately 2 nm in both generations, TSMC has traded speed and raw performance for reduced leakage and power in this version of its process.

Design choices
In comparison, the Nokia 4377401 processor was fabricated in Texas Instruments' competitive 65-nm low-power CMOS process technology and comes in a Nokia package. Like the TSMC process, TI uses a six-level Cu interconnect process, with a top Al layer and OSG low-k intermetal dielectrics. TI has also introduced technologies similar to what TSMC introduced at 65 nm, including Ni-silicide and strain engineering to improve both N- and P-MOS transistor performance. The TI 65-nm process technology is reported to shrink the 90-nm design area by half, leverage strained silicon to boost transistor performance by 40 percent and reduce leakage power from idle transistors by a factor of 1,000.

The design strategy appears to diverge when comparing the significant difference between the die sizes of the Qualcomm and Nokia devices. But one must consider that they are also significantly different in function. Qualcomm has apparently opted for increased functionality and reduced form factor at the expense of reduced flexibility in process design optimization. On the other hand, TI has chosen to maintain some flexibility by decoupling the process and design interactions likely to allow more independent optimization. This would require more separate devices to be used in the multichip package than the integrated approach would, depending on the system functionality desired.

Going forward
Semiconductor manufacturers introduced a number of new techniques at the 65-nm technology node. Notably, these introductions were strain engineering for increased mobility and Ni-silicide to enable ultrashallow junction architecture.

These processes enabled advances in wireless multimedia product designs, resulting in an increased transistor count per unit area and reduced power consumption. But these are merely evolutionary techniques that are meant to bridge the 45-nm node gap. It will be interesting to see what innovative design techniques are used to fully realize a 45-nm solution.

John Boyd (johnb@semiconductor.com) is product technology manager, process, at Semiconductor Insights, a semiconductors analysis firm in Kanata (Ontario). Boyd was a founding member of SI's original Process Analysis group in 1995. After that, he worked at Lam Research and at Nortel. He holds more than 60 U.S. patents and has more than 40 pending applications.