EE Times: Semi News
ALD takes one step forward, one step back
(08/10/2006 8:30 AM EDT)
SAN JOSE, Calif. — Atomic layer deposition (ALD) continues
to make major inroads — and has stalled — in living up to its promises
of becoming an enabling technology for mainstream chip production.
Call it a story of the good, bad and ugly. For some time, DRAM makers have successfully used ALD technology as a means to scale the capacitor in a memory device.
But on the copper/barrier seed front, ALD has been pushed out to the 32-nm node. And due to a possible delay for high-k dielectrics in logic designs, ALD has stalled as the deposition technology of choice.
ALD, which has been around for decades, deposits ultra-thin films one atomic layer at a time. Unlike conventional deposition technologies, ALD offers control of the thickness and uniformity of monolayer films of less than 100 angstroms.
In total, the ALD equipment market is projected to grow 23.1 percent, from $172.4 million in 2005 to $487.3 million by 2010, according to a report from Robert Maire, an analyst with Needham and Co. LLC. Among the equipment players in ALD include Applied Materials, ASMI, Aviza, Genus, IPS, Novellus, TEL, Veeco and others.
ALD has been a smash hit in DRAMs. At one time, DRAM makers were using conventional techniques to deposit silicon dioxide or oxide-nitride-oxide (ONO) dielectric materials for capacitor applications.
Then, starting at the 130-nm node, South Korea's Samsung Electronics Co. Ltd. was said to be the first DRAM maker to deploy high-k dielectric films via ALD for stack capacitor applications.
Other DRAM suppliers followed suit. In this application, capacitor area decreases with each technology node, forcing DRAM makers to deploy high-k films via ALD, said Subrata Chatterji, vice president and general manager at ALD Business Unit at Aviza (Scotts Valley, Calif.).
Now, DRAM makers have a new requirement, which, in some cases, is the Achilles' heel for suppliers of ALD gear: higher throughput. Many DRAM makers are using single-wafer ALD tools, which deposit highly conformal films — sometimes at the expense of throughput.
"People are now moving from single wafer to batch," said Chatterji. "Throughput continues to be a challenge with single wafer tools. But the challenge with batch is whether or not all of the new materials can be handled in a batch environment."
Aviza sells a batch-enabled ALD tool. In May, Aviza introduced its next-generation, single-wafer ALD machine and said that the company has shipped one these products, apparently to Chinese silicon foundry provider Semiconductor Manufacturing International. Corp. (SMIC).
Aviza said the system, dubbed Celsior, is aimed at the 90-nm node and beyond. It is built on a platform that was acquired through a joint-development partnership with Trikon Technologies prior to Aviza's acquisition of that company last December.
Celsior features a new chamber, which, according to Aviza, lowers the tool's cost of ownership by offering increased throughput, lower chemical consumption and an extended process window. The tool utilizes a patented showerhead designed to meet stringent ALD process needs, including less than 1 percent thickness uniformity requirements across a 300-mm wafer, Aviza said.
ALD was invented with little or no fanfare in the mid-1970s, but it wasn't until 2003 when the technology made big headlines. Faced with intolerable levels of wasted power in its microprocessors, Intel Corp. in 2003 said it will make the switch to a high-k gate insulator in 2007, reducing current leakage at the gate by at least 100 times.
At the 45-nm process node, Intel said it would make a double switch, replacing the tried-and-true silicon dioxide with an unidentified high-k insulator. Rather than grow the insulation layer as is commonly done with silicon oxide, Intel said it would use ALD equipment to deposit the high-k materials.
It is also widely believed that Intel would use ALD equipment from one of its key tool suppliers: ASM International N.V. of the Netherlands.
Since the big announcement three years ago, however, Intel has been mum about its efforts with high-k, not to mention ALD. Officials from Intel have repeatedly declined to comment on its efforts with high-k, leaving questions about the viability of the technology at the chip giant.
Perhaps Intel is having trouble with high-k. Maybe the chip maker doesn't want to telegraph its high-k secrets and is keeping its cards close to the vest.
For gate-stack applications in the logic space, others are delaying high-k at the 45-nm node, namely Texas Instruments Inc.
Indeed, there is considerable confusion over the deployment of high-k dielectric films for gate-stack applications at the 45-nm node and beyond. And there's even more questions surrounding the plethora of material candidates — and deposition techniques — used for high-k.
On the high-k materials front, "I don't think there is a consensus in the industry," said Aviza's Chatterji. "There is a lot of confusion."
One of the challenges with high-k is the integration process. Current polysilicon electrodes are not compatible with high-k films. "With high-k, there will be several challenges," said Gary Miner, chief marketing officer for the Front End Products Group at Applied Materials Inc. (Santa Clara, Calif.)
Last year, Applied Materials dropped hints about entering the metal organic chemical vapor deposition (MOCVD) equipment market. Applied is also expected to make its long-awaited entry into the ALD tool market for gate-stack applications.
Chip makers hope to replace silicon dioxide materials with new and complex high-k dielectric films by using a variety of competitive tool technologies, such as ALD, MOCVD, chemical vapor deposition (CVD), among others. And device manufacturers also face other tough choices in terms of using single- or batch-wafer tools.
In the back-end-of-line (BEOL) segment, ALD has seen its share of hype, especially for copper/barrier seed applications. In 2002, for example, Applied Materials entered the ALD market, announcing a tool that enables new and advanced films for chip designs at the 65-nm node and beyond.
Applied took an integrated approach to the emerging market. The company's tool, dubbed the Endura iCuB/S, is an integrated ALD and physical-layer deposition (PVD) system for 300-mm fab applications.
The tool, which is still in Applied's product portfolio, is based on its Endura XP mainframe tool line. The tool enables copper-based chip designs, with tantalum nitride (TaN) barrier layers that are compatible with advanced low-k dielectric films.
For copper/barrier seed applications, Applied at the time dropped hints that ALD would be inserted at the 90-nm node — at the expense of PVD.
Applied's assertions that ALD would displace PVD proved to be too optimistic. "At the time, we said: 'I don't think so,' " said Jeffrey Benzing, executive vice president and chief business officer at Novellus Systems Inc.
PVD continues to extend beyond the 90-nm node in the copper/barrier seed arena, thereby pushing out ALD to the 32-nm node, Benzing said. "We've pushed PVD technology," Benzing said in a recent interview. "We've pushed it to 45-nm."
"This is not to say that Novellus has dismissed ALD," said Needham's Maire. "On the contrary, the company is hedging its bets if or when PVD is running out of steam."
Last year, Novellus announced the Inova Next, a 300-mm metallization system for copper barrier/seed applications at the 45-nm node and beyond. An extension of Novellus' Inova PVD platform, the Inova Next enables PVD and ion-induced ALD (iALD) on the same system.
The tool's single-target hollow cathode magnetron PVD technology has been extended to the 45-nm node. In theory, the iALD TaN film replaces PVD TaN as the barrier layer for copper, providing a reduction in line resistance due to the highly conformal and ultra-thin nature of the film. The ALD technology is based on R&D from Angstron Systems Inc., which was acquired by Novellus in 2004.
All material on this site Copyright © 2006 CMP Media LLC.
All rights reserved.
Privacy Statement | Your California Privacy Rights | Terms of Service