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Copper Challenges for the 45 nm Node
At a Glance
Look for changes in diffusion barrier technology, bath additives, capping layers, and the integration of porous ultralow-k dielectrics in the near future.

As the industry heads toward the 45 nm node, some changes in copper processing technology are imminent. We're likely to see TaN diffusion barriers deposited by atomic layer deposition (ALD) instead of physical vapor deposition (PVD). This could be followed by the introduction of ruthenium barriers, which would eliminate the need for a seed layer, but this will hinge on the results of research presently underway.

A change in the organic "additives" in the plating bath is also a possibility, since some of these additives wind up embedded in the copper. Manufacturers use additives to get seam-free filling without excessive copper overburden in dense areas, which makes chemical mechanical planarization (CMP) less difficult, but embedded impurities raise resistivity and make it difficult to get desirable larger grain sizes when the copper is annealed.

A serious reliability problem, electromigration most often occurs on the top of copper lines, at the interface with the dielectric. A possible solution is the selective deposition of cobalt tungsten phosphide (CoWP) or cobalt tungsten boride (CoWB) onto the copper (and eventual replacement of the Si(C)N layer), which acts as a capping layer to "lock" the copper into place. An alternative is to treat the copper so that it better adheres to the overlying nitride or SiC layer.

Electron scattering from grain boundaries, defects and surfaces will also become an increasing problem in that it leads to higher resistances in lines with very small dimensions. Solutions could include larger grain sizes, reduced defects and atomically smooth surfaces.

Of course, at some point copper will need to be integrated with porous ultralow-k dielectric materials, which will add yet another degree of complexity to copper processing. Just one of the problems is that these porous materials will require some kind of pore sealing process, and there is concern as to how they interact with the diffusion barrier that is deposited upon them.

Copper basics

The main advantage of copper remains the same as it was in the mid-1990s when IBM, Intel, AMD and other IC manufacturers decided to make the move to copper from aluminum. It has better conductance (lower resistance), which means interconnect lines can be smaller and packed more tightly, yet still have the same (or better) current carrying capacity. They can also be thinner, which reduces crosstalk between lines. Lower resistance also means higher chip speed in that the "R" part of RC (resistance capacitance) time delays are reduced. Reducing the "C" part of RC delays is the reason why there's interest in using low-k for the insulators that surround the metal ("k" is the material's dielectric constant or permittivity, which is a measure of its ability to carry a charge).

Although there is a lingering perception that copper is a "tricky" process, due in part to early reliability problems, every company in the world now manufacturing 130 nm logic devices is using copper, according to Dan Hutcheson, president of VLSI Research Inc. (San Jose). The process is well understood and yields are high, in some cases higher than equivalent aluminum processes. On the other hand, as companies race toward the 65 and 45 nm technology nodes (45 nm is scheduled to be in production in 2013), it's clear that the copper manufacturing process will need to be tweaked in several areas, ranging from the way diffusion barriers are deposited to the type of capping layers used. Although delayed, ultralow-k dielectrics are also expected to be implemented in this timeframe. This will mean many new materials and, the fear is, perhaps some unforeseen reliability problems, which often occur at the interfaces of unlike materials.

It should be noted that aluminum hasn't gone away. On the contrary, it remains the material of choice for a variety of devices, most notably DRAMs, which have only a few levels of interconnects and operate at slower speeds than logic devices. DRAM manufacturers are continuing to make advances in aluminum technology, including the use of aluminum ALD and CVD, according to Hyunchul Sohn of Hynix Semiconductor (Seoul, Korea). Although there could come a day when copper will prove to be a less expensive manufacturing process than aluminum, that day isn't likely to come soon, Sohn said.

The copper process is entirely different from that of aluminum. Aluminum is typically blanket-deposited and etched, followed by the deposition of an insulating dielectric (which can involve filling what are sometimes high-aspect-ratio gaps between the metal lines). Copper, on the other hand, is patterned in a way named after the ancient inlaid metal technique that originated in Damascus: damascene processing. Lines are connected to the underlying and overlying lines by vias. The holes that are etched to create these vias require a separate masking and etch step, which gives rise to the name "dual-damascene."

In dual-damascene processing, the dielectric is first blanket-deposited. Holes and channels are then etched into the dielectric (this involves two lithography steps and possibly a hard mask). Next, a diffusion barrier is deposited (copper is a known fast diffuser, and will move quickly through the dielectric and "poison" a device if it is not contained by the barrier). This is followed by the deposition of a copper seed layer. This seed layer is necessary for the electrolytic deposition of copper from a plating bath, which is typically known as copper "fill." After an annealing step, the copper is planarized. After the copper is planarized and cleaned, a layer of silicon nitride (Si3N4) or SiC is deposited, a layer of dielectric blanket-deposited, and the whole process starts over. The purpose of the Si3N4 or SiC layer is that it acts as a hard mask during subsequent via etch; some vias are not lined up perfectly with the underlying metal (i.e., they are unlanded) and a hard mask prevents the etching of pockets down the side of the metal.

Copper lockdown

One of the main concerns regarding copper as the industry drives to the 65 and 45 nm device generations and beyond is to not degrade the current carrying capability of copper lines. The "magic number" for conductor effective resistivity is 2.2 V-cm, defined by the International Technology Roadmap for Semiconductor (ITRS).1 As lines shrink, this becomes more difficult for two reasons. First, as dimensions of the line start nearing the mean free path of electrons in copper (39.3 nm), electron scattering begins to become more of a problem. "Line and via sidewall roughness, intersection of porous low-k voids with sidewall, barrier roughness, and copper surface roughness will all adversely affect electron scattering in copper lines and cause increases in resistivity," the ITRS notes. This may eventually force a move from copper to another approach to interconnects, such as RF or photonic waveguides, but that is years away. In the meantime, the focus will be on keeping grain size large and keeping surfaces as smooth as possible.

1. SEM image of copper interconnects on Intels 90 nm process generation. The liner film consumes ~15% of the interconnect cross-sectional area. (Source: Intel)

A second and more immediate concern is that, as lines shrink, PVD-deposited copper barriers cannot be made thinner. "The cross section occupied by the barrier is becoming a larger percentage of the cross section relative to the copper, which is actually conducting the current," noted John T.C. Lee, general manager of Applied Materials' Maydan Technology Center. At the 65 nm node, for example, copper lines are ~900 wide and 1500 high, but the diffusion barrier consumes about 300 on the bottom and 100 on each side. This means that a cross section of a line that could be 13,500 nm2 in area is only 8400 nm2 in area. "That's a huge impact on the effective line resistance," said Wilbert van den Hoek, CTO and executive vice president of integration and advanced development at Novellus Systems (San Jose). Figure 1 shows that 15% of the copper interconnect line is consumed by the barrier in Intel's 90 nm process.

The solution is to use a thinner copper barrier, and the best approach is an ALD-deposited barrier. Work on this technology has been underway for some time, and commercial tools have recently become available.2,3 "We've gotten to a point where the solution is pretty much narrowed down close to something that's going to be workable," Lee said. Figure 2 shows how ALD barriers can achieve much lower resisitivity than PVD barriers.

2. Compared with PVD-deposited barriers, ALD barriers offer consistently lower line resistance. The ITRS calls for 2.2 Ω-cm through at least 2018. (Source: Applied Materials)

Work has focused on ALD TaN, in name, the same as the PVD TaN films used presently. However, while PVD TaN is really nitrogen-doped tantalum, TaN0.5, with a resistivity <200 Ω-cm, ALD TaN tends to be a stochiometric TaN. The high nitrogen content and the amorphous structure are responsible for the barrier properties of this film. However, typically, organometallic precursors are used and, depending on the precursor choice, residual carbon can be an issue, and carbon concentrations from 2 at% up to 10 at% have been reported. With ~10 at% carbon, the film is TaN0.09C0.1 with an unacceptably high resistivity of 1 mΩ-cm. "Organo-metallic precursors are used, and it is fairly difficult to get all the carbon out," van den Hoek said. "With some approaches, you deliberately leave a larger amount of carbon in and then you make a nitrogen-doped tantalum carbide (TaC0.4N0.6) with a resistivity of ~250 V-cm." An example of a precursor used to deposit copper barriers by ALD is TBTDET (tert-buthylimidotrisdiethyl- amidotantalum).

From an integration standpoint, the ALD TaN approach appears the most straightforward because it represents the least amount of material change. "ALD TaN films have demonstrated reduced line resistance," Applied's Lee commented. "Ongoing work is focused on validation of process integration to meet reliability requirements."

Ruthenium to the rescue?

An interesting tradeoff for the PVD-deposited copper seed layer is this: It needs to be thin enough to avoid the overhang at the top of high aspect ratio features, which can pinch off and create voids. But it can also be too thin. "Copper tends to oxidize readily in atmosphere and copper oxide readily dissolves in the plating solution. If you make the copper too thin, the copper will fully oxidize," van den Hoek said. "When you put it in the plating solution, the copper oxide dissolves and you get a discontinuous seed. With a discontinuous seed you get voids in the plated copper." Another problem with a thin copper seed layer is that there will be a very large voltage drop between the edge of the wafer and the center of the wafer, resulting in very non-uniform plating, he added.

One solution being evaluated is to plate copper directly onto a diffusion barrier. Ruthenium, in particular, has shown great promise in this area (see "Transition Metals Show Promise as Copper Barriers "). Not only could ruthenium potentially replace a two-step Ta/TaN process commonly used for diffusion barriers, but it could replace the seed layer as well. Since ruthenium is conductive, copper will electrolytically plate onto it. "Ruthenium is a very attractive material because it's a near-noble metal," van den Hoek said. "It doesn't oxidize readily, but if it does it forms ruthenium oxide, which is also a conductor." Another advantage is that ruthenium enables plating in standard plating chemistry. "You get the same acceleration and plating behavior with existing plating chemistries on ruthenium as you get on copper."

There will be several challenges to resolve, according to Lee. The replacement of a ~1200 copper seed film with a ~100 ruthenium film will effectively raise the sheet resistance of the seed ~100 because of thickness and inherent resistivity changes. Plating uniformities and nucleation characteristics will need to be revalidated. "Device reliability is largely driven by interface make-up and integrity ruthenium film composition, morphology, adhesion characteristics are likely to require optimization to meet stringent SM and EM requirements," he said.

Plating copper on very thin seed layers at sub-65 nm raises several critical issues. "We find that the first few seconds of plating can determine the success of the copper fill," said Russell Ellwanger, vice president and general manager of Applied Materials' planarization and plating products. "It is important to wet the seed layer uniformly by controlling the angle of wafer immersion, which enables the elimination of immersion defects or trapped microbubbles. Also, total defectivity on the wafer becomes increasingly important. Certain defects caused by the copper plating process, especially those initiated during the first seconds of plating, are not polished off during the subsequent planarization process and can affect yield."

As far as replacing both the diffusion barrier and the seed layer with one ruthenium film, some questions remain. "For awhile there was hope that ruthenium would be an adequate barrier, but at this point, most people have come to the conclusion that thin ruthenium is probably not adequate as a barrier," van den Hoek said. Instead, he believes the solution will be to deposit an ALD barrier, followed by an ALD ruthenium process. "But you have to keep that whole stack down to preferably fewer than 50-70 to minimize the impact on line resistance."

Another proposed solution to the problems of holes in the seed layers is to repair them with an electroless plating technique (also called seed layer enhancement, or SLE). This results in picture-perfect copper fill, but some question how well the repair adheres to the underlying barrier, raising concerns about electromigration voids and failures at that point.

Suppressors, accelerators, levelers

The main objective of the electroplating process is to deposit copper that is dense, free of voids, "seams" and other defects, and with good uniformity across the wafer. This is often compounded by the need to fill dense, high-aspect-ratio features and vias, while also filling larger, open features. It's also desirable to leave the surface as planar as possible, to minimize subsequent problems with CMP, most notably dishing and erosion (Fig. 3 ). "Because gapfill performance relies heavily on electroplating bath chemistry, a consistent chemical environment for each wafer is important," Ellwanger said. "The organic additives break down during the plating process and accumulate in the plating bath. This makes it increasingly critical to minimize additive breakdown and product buildup in the plating bath for production consistency." A common problem for CMP is overplating or overburden, where copper builds up on top of dense arrays of features.

3. Copper CMP must often deal with large overburdens over densely packed lines, while minimizing the negative impact of dishing and erosion. (Source: Lam Research)

A copper electroplating solution is typically made up of copper sulfate (CuSO4), sulfuric acid and water (the CuSO4 gives it a bluish tint). An ideal fill process starts off as conformal, with copper depositing equally on the sides and bottom, then quickly switches to a bottom-up fill to avoid seams and voids. Two organic additives are also used to achieve these results: a suppressor and an accelerator. When a wafer is first immersed in the plating bath, conformal filling of the structure begins. Filling kinetics are controlled by the suppressor. Next, the transition from conformal fill to bottom-up filling occurs as the accelerator reaches a critical concentration.4 The accelerator, a polymer/chloride complex, absorbs on the copper surface and lowers the electrochemical potential for the plating reaction, promoting faster deposition.

The problem here is that the accelerator doesn't stop when the feature is filled, but floats on the top and continues to promote copper deposition. Since narrow, dense features fill faster than wide, open features, this can lead to overplating or extra overburden. The solution is a third additive: a leveler that causes desorption of the accelerator. This works well, the only problem being that the leveler, unlike the accelerator, can become incorporated in the copper. "What's happened is we've gone to higher concentration of leveler to address this overplating problem, and the downside is that you get more contamination in the copper," van den Hoek noted. The good news is that new levelers have been identified that will do the same thing but don't get incorporated into the copper.

"Emerging requirements for wetting of 300 mm substrates, plating smaller and smaller vias, increasing purity requirements and delivering void- and defect-free plating for the 45 nm node, for example, require continual improvements to the individual functional performance for each of the organic accelerator, suppressor and leveler, as well as balancing their performance as a package in the electrolyte bath," said Mike Rousseau, EP-Cu marketing manager for Rohm and Haas Electronic Materials' Microelectronic Technologies Division (Marlborough, Mass.). "Additive packages that worked at the 130 nm and even 90 nm node are not going to meet these more aggressive performance targets."

Electromigration, selective CoWP

It was once thought that copper had good resistance to electromigration better than aluminum. As it turns out, exactly the opposite is true, at least for very small geometries. Electromigration is a well known reliability problem with aluminum, caused by electrons pushing and moving aluminum atoms to a point where a void occurs, increasing resistivity, or even a line break. Once understood, it was easily controlled by adding small amounts of copper to the line and by depositing the aluminum with a columnar grain structure. Because it's a bulk phenomenon, the smaller the line, the easier it is to control.

Electromigration in copper, on the other hand, is a surface phenomenon. It can occur wherever the copper is free to move, typically at an interface where there is poor adhesion between the copper and another material. In today's dual-damascene structure, this happens most often on the top of the copper line where it interfaces with what is typically a SiC layer. "If you don't do that interface engineering correctly, it's a weak point," noted Lee of Applied Materials. "If you have a weak interface, it can start a chain reaction, where copper atoms move and suddenly you have a void and an electromigration failure. Unlike aluminum, the smaller the line, the bigger the problem.

One solution is to treat the copper surface to get better adhesion to the SiC. This typically involves using the silane from the SiC deposition process, which can be tricky because the silane could penetrate into the copper, raising resistivity. Another approach is to selectively deposit a cobalt-based film on top of the copper, typically CoWP or CoWB. This works very well, offering a 10 improvement in electromigration resistance (Fig. 4 ). But there are several concerns: 1) It changes the planarity of the surface, unless the copper is already recessed after CMP; 2) it adds an extra processing step, which can be costly; and 3) it's a selective process, which could potentially be tricky if, for example, some copper residue were left on the open areas of dielectric. "Capping the copper with CoWP has demonstrated device reliability improvements, which also results in higher device performance at 65 nm, the addition of a cap layer allows current density to be dramatically increased, and IC manufacturers are looking at lowering the effective k value at 45 nm by eliminating the etchstop dielectric layer," said Igor Ivanov, CTO of Blue29 (Sunnyvale, Calif.), a supplier of electroless deposition solutions.

4. Copper electromigration data shows 10 better reliability for copper with a cobalt cap layer relative to a conventional
Si(C)N cap. (Source: Intel)


Low-k integration

The challenges of integrating low-k dielectrics are well known or at least well publicized. This was emphasized in the latest ITRS, which indicates a delay of low-k introduction. "Even with new ever more stringent requirements for future technology nodes, the lifetime of the existing class of dielectric materials has been extended because of problems with the properties or integration of the new materials," notes the ITRS. Early on, the industry moved from SiO2 to fluorinated silicate glass (FSG), and then on to true low-k materials, including carbon-doped oxides and polymer-based spin-ons.5,6 By the 45 nm node, however, the industry is expected to face the real challenge: integrating ultralow-k materials, which are generally porous.

One problem with porous ultralow-k dielectrics is that the pores tend to readily absorb water or other chemicals, so they need to be sealed. Various pore sealing approaches have been tried, but it appears that for any to work well, the pore size needs to be below 2 nm (see "Effective Pore Sealing of Ultralow-k Dielectrics " for one such approach). Another problem is that they have less rigidity, requiring less pressure during CMP, or perhaps low-pressure CMP combined with a stress-free polishing approach, where the copper is first planarized and the bulk of it removed by reverse electroplating.


 


References
  1. International Technology Roadmap for Semiconductors (ITRS), http://public.itrs.net/.
  2. L. Peters, "Making a Better Copper Barrier ," Semiconductor International , March 2003.
  3. A. Hand, "Industry Begins to Embrace ALD ," Semiconductor International , May 2003.
  4. M. Rousseau, "Advanced Plating Chemistry for 65 nm Copper Interconnects ," Semiconductor International , May 2003.
  5. A. Braun, "Low-k Integration Advances With Hesitation ," Semiconductor International , May 2003.
  6. L. Peters, "Removing Barriers to Low-k Dielectric Adoption ," Semiconductor International , May 2002.