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INDUSTRY NEWS

Chipworks Corner

IBM, AMD use different dual-stress liner
techniques for channel strain

At the 2004 IEEE International Electron Devices Meeting (IEDM) in San Francisco, AMD and IBM jointly presented a paper on a dual-stress liner (DSL) technique for straining both the NMOS and PMOS transistor channels in their 90-nm processes. IBM had previously utilized the nitride liner layer (also known as a contact etch-stop layer) on a transistor to apply tensile stress to the NMOS channel and used a relaxation implant to relieve the stress over the PMOS channel.

The effect of compressive stress on PMOS performance enhancement was already well documented; Intel had claimed 50% improvement using its method of embedded silicon-germanium source/drains to apply compressive stress to PMOS devices. However, the integration of this technique poses a significantly more complex challenge than tuning the nitride deposition.

As I well remember from my earlier years, nitride layers are notorious for the way that their inherent stress reacts to processing conditions (some wafers came out of the reactor like Pringles chips!). So it is a logical step to tweak the process to give a liner layer a compressive stress, thereby increasing the hole mobility and improving PMOS performance.

The AMD/IBM paper described precisely this kind of approach. After transistor formation, a tensile nitride layer is laid down, masked, and etched off the PMOS regions. A buffer (mask) oxide is deposited, and then a compressive nitride layer is put down, masked, and etched off the NMOS areas. The paper claimed a 12% performance increase for an Athlon product and 7% for an IBM microprocessor that were made using the technique.

As a result of the paper, Chipworks was on the lookout for DSL chips. The first one procured was an AMD Athlon 3500 Venice processor. To our surprise, we found something very different from what was described at IEDM.

Figure 1 is a SEM image of SRAM transistors stained with an oxide etch. The 80-nm-thick silicon-on-insulator (SOI) island shows up nicely, but it is obvious that something bizarre has happened in the NMOS transistors since nitride doesn’t normally etch like that. The TEM shots of the NMOS and PMOS transistors in Figures 2 and 3 reveal several observable differences. The NMOS nitride liner has a more diffuse image density in the top half of the layer than the PMOS liner layer. Figure 4 shows the edge of the diffuse region over a gate edge, and there is clearly no sign of the mask/etch steps detailed in the paper; AMD has found a way of making a DSL layer using a single nitride deposition.

Figure 1
Figure 2
Figure 3
Figure 4

The transistors can be seen to have AMD’s characteristic triple-spacer structure, evidence of the complex source/drain engineering that the company uses. Note the stacking faults under the NMOS inner spacer, presumably a result of a heavy drain extension implant. Energy-dispersive x-ray analysis of the different parts of the nitride layer revealed that the difference was in oxygen content: looking at the shape of the diffuse region, it appears that there was a fairly hefty oxygen implant in the NMOS areas.

We’ve concluded that a compressive nitride layer was put down across the whole wafer, the PMOS regions were masked, and then oxygen was implanted into the NMOS regions. With an appropriate anneal, part of the nitride layer is converted to oxynitride, changing the stress from compressive to tensile over the NMOS devices. A back-of-the-envelope calculation shows that 6 × 1016 atoms/cm2 of oxygen into a depth of 50 nm gives an oxygen content of ~10%, surely enough to modify the stress in the liner layer.

The DSL process described at IEDM was brought to fruition by the AMD/ IBM joint development group at East Fishkill, NY. It appears that the AMD guys in Dresden liked the concept, but decided that the extra deposition and masking steps were not worth the effort, so they thought up this more elegant way of achieving the same effect.

It took a little longer to track down an IBM DSL part, but one turned up on the central processor chip in the Microsoft Xbox 360. Figures 5 and 6 are TEM images of the NMOS and PMOS transistors, respectively, each with its distinct structure. Figure 7 shows the overlap area of the two layers.

Figure 5
Figure 6
Figure 7

The NMOS has had the sidewall spacers etched back to get the stress closer to the gate edge (and reduce source/drain series resistance), but by contrast the PMOS has full spacers plus a buffer layer before the stress liner deposition. The compressive nitride is composed of many very thin sublayers, and the overlap region has an oxide mask/buffer layer. IBM is using a thinner 50-nm-thick SOI active layer.

At the recent Advanced Semiconductor Manufacturing Conference in Boston, IBM revealed some of the problems they faced integrating the dual layers into the process. The contact-etch process needed considerable tuning, and weakness and voiding were induced in the premetal dielectric, which caused cracking and shorts between contacts. These problems were solved by tuning the deposition of the premetal dielectric layer and modifying the tensile nitride-etch process to improve the subsequent profile of the compressive layer.

Reports have circulated that IBM has also moved to a single-layer process, but we have yet to see any devices incorporating this approach. Since the advent of process-induced strain in front-end processing, a variety of different ways have been used to apply the stress. Since gate dielectrics will remain stuck at 12–15 Å thick until high-k dielectrics are finally introduced, strained transistors offer a method for improving performance in the interim.

These two devices offer good examples of the “many ways to skin a cat” evolution of strain engineering, achieving the same objective by different methods. As we move further into the 65-nm era and beyond that to 45 nm, the development of other techniques will likely be seen. —Dick James

This report is one of a regular series of device-level process analyses, written exclusively for MICRO by Chipworks’ senior technology analyst, Dick James, a 30-year veteran of the semiconductor industry. Chipworks is an Ottawa, ON, Canada– based specialty reverse engineering company that gets inside technology and takes apart ICs and electronics systems in order to provide engineering information for its customers. The technical intelligence customers are usually within manufacturing companies, performing product development, or doing strategic marketing or benchmarking studies. The patent intelligence clients are usually patent lawyers or intellectual property groups within manufacturing companies.