Semiconductor & Patent Expert Consulting

Litigation expert consultant and patent expert witness for process, device, and circuit of  Dynamic

 Ram (DRAM), Flash  (NAND, NOR, EEPROM), and Static Ram (SRAM) Memories,

 and Microprocessor, Logic, and Analog Devices




Chipworks' analysis finds high-k, recessed transistors in Samsung's SDRAM

The 90-nm era truly came of age in 2004, according to a presentation at the recent Advanced Semiconductor Manufacturing Conference (ASMC) in Munich. Dick James, Chipworks' senior technology analyst, showed how device specifications from Intel, IBM, AMD, Fujitsu, TI, and Sony/Toshiba as well as fabless-customer designs manufactured by UMC, TSMC, and Fujitsu compared with the International Technology Roadmap for Semiconductors (ITRS) and the respective companies' published data.

Chipworks' structural analyses found that none of the devices matched or exceeded the metal-1 half-pitch or the minimum gate-length dimensions for the 90-nm node established in the roadmap's 2003 edition. As James pointed out during his presentation, "In practice, a node is a consensus of what the leading-edge manufacturers actually do in their chips, not what's defined in the ITRS." While the half-pitches analyzed were found to be both larger and smaller than the companies' published data, all of the samples examined had smaller gate lengths (ranging from 40 to 55 nm) than the chipmakers' publicly shared numbers. The 90-nm analyses also confirmed the introduction into production of strained silicon using the uniaxial method.

One of James's reverse-engineering studies barely made it into his ASMC presentation: Samsung's 512-Mb DDR SDRAM chip, which debuted at the end of 2004 as the industry's first mass-produced 90-nm device of its kind. "In this chip," he notes, "Samsung has introduced some significant process innovations into mass production: the first recessed transistor in a DRAM, the first use of an aluminum/hafnium oxide high-k dielectric, and likely the first mass usage of atomic layer deposition (ALD)." In a MICRO exclusive, James details what he and his colleagues discovered during their analyses of the Korean chipmaker's innovative device. 

Figure 1

"The device has a conventional stacked capacitor-over-bitline (COB) architecture for the memory arrays (see Figure 1). It is fabricated using three levels of metal and six polysilicon layers. The part features 70-nm-wide gate polysilicon for the recessed-channel transistors in the DRAM array, and the minimum-pitch metal 1 is 180 nm, making it a true 90-nm product according to the ITRS definition.

"The device includes significant technical changes, such as a high-k aluminum/hafnium oxide dielectric layer in the storage cell and recessed word-line transistors in the array. These changes. . .were originally targeted for the 80-nm node, but it seems that Samsung is happy enough with the technology to bring it forward into its 90-nm product.

Figure 2

"The die size is a compact 68 mm2. Figure 2 shows a cross section taken in the plane of the bitline and offers a clear image of the recessed channel array transistors (RCATs) used for the word-line transistors in this part. The concept of the RCAT is to increase Leff by recessing the channel from the silicon surface, thereby reducing leakage and enhancing data storage characteristics. The physical gate length in the surface plane is ~70 nm, but the effective channel length is ~350 nm (which compares with the ~90-nm channel length of a 130-nm SDRAM part).

"Samsung literature discloses the use of 193-nm [ArF] lithography with a polysilicon hard mask to define the trenches, followed by a steam oxidation to form the gate oxide. Close examination of the image shows that the gate-oxide thickness varies from ~7 nm at the trench bottom to ~14 nm on the trench walls, presumably because of the different oxidation rates of the different crystal orientations. The company claims that the RCAT structure reduces array junction leakage by more than an order of magnitude. There also seems to be a thin nitride layer in the shallow-trench isolation, again possibly to reduce leakage by reducing strain in the substrate.

Figure 3

"Moving on to the capacitor structure, Figure 3 is a TEM cross-sectional image of the tops of a pair of the cylindrical capacitors in the memory array. The "tuning fork" structures are the tops of two storage nodes, and the microgranular texture around and between them is actually the titanium nitride (TiN) layer used as the first layer of the common plate in the array. Polysilicon is then deposited on this TiN layer to fill in the gaps between the storage nodes and complete the capacitor.

Figure 4

"Figure 4 is a horizontal TEM section through the array, clearly showing the cylindrical nature of the storage nodes. The annular dark circles are again the TiN layer on the inner and outer surfaces of the tuning forks. A notable feature at this scale is the differing distances between adjacent capacitors, created when the sacrificial oxide (used for the formation of the cylinders) is removed. Figures 5 and 6 provide closer looks at the capacitors, where the dielectric layers on the inside and outside surfaces of the capacitors can be seen.

Figures 5 and 6

"A feature that surprised us was the variable crystalline nature of the silicon in the top capacitor plate. In almost all cases, the silicon inside the cylinders is amorphous, while outside the cylinders it is sometimes polycrystalline and sometimes amorphous. Figure 6 shows the bilayer nature of the capacitor dielectric—the aluminum oxide has been deposited first, then there is a thinner, darker line which is the hafnium oxide. These layers—and the TiN—have been formed by ALD, probably one of the first high-volume applications of this technique."—TC