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IEDM 2008 - Update


1.TSMC tips 32nm high-k; IBM adds 'k' to FinFET / EETimes

2. Flash memory at the 'crossroads' / EETimes

3.IBM gives update on STT-based MRAM/ DigiTimes

4. Latest 32nm Process, Memory Beyond Flash, and Novel Devices - 2008 IEDM - Solid State Technology



1. TSMC tips 32nm high-k; IBM adds 'k' to FinFET

SAN FRANCISCO -- At this week's International Electron Devices Meeting (IEDM) here, IBM, Intel, TSMC and the NEC/Toshiba duo will separately present papers on 32-nm processes with high-k and metal gates.

The biggest surprise is silicon foundry giant Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), which isn't supposed to have its high-k/metal-gate solution ready until the 28-nm node.

IBM's ''fab club'' has recently disclosed the details of its 32-nm process with high-k and metal gates. This week, the group will present a paper on a 32-nm FinFET with a high-k/metal-gate scheme.

Also at IEDM, the NEC/Toshiba duo will present a ''cost-conscious'' high-k/metal-gate scheme. Last week, Intel Corp. rolled out its 32-nm process, based on a second-generation, high-k/metal-gate scheme.

There are two basic approaches to the next-generation gate stack in logic designs. IBM's ''fab club'' is using a gate-first approach to the high-k/metal-gate scheme, while Intel is deploying a rival replacement-gate technology. In a gate-first approach, the gate stack is formed before the source and drain, as in a conventional CMOS process. Replacement-gate technologies are a gate-last approach, where the gate stack is formed after source and drain.

At IEDM, TSMC will present a paper about a 32-nm process, which includes a high-k/metal-gate scheme based on a gate-first technology. A 0.15-micron2 SRAM cell was developed by using a hafnium-based material and 193-nm immersion lithography with a numerical aperture of 1.35, according to TSMC's paper.

TSMC's high-k material has been scaled to 10 angstroms. ''Drive currents of 1340/940-uA/um are achieved at Ioff=nA/um, Vdd=1V, 30-nm physical gate length and 130-nm gate pitch,'' according to the paper.

It's unclear if TSMC will offer the technology at 32-nm, however. The company said it plans to roll out high-k at 28-nm, which TSMC considers as its ''full-node'' technology.

In a separate paper, the team of NEC Corp. and Toshiba Corp. disclosed that it has developed a 32-nm process, with a single-exposure lithography technology and a ''gate-first'' high-k/metal-gate process. The chip makers have demonstrated a SRAM cell of 0.124-micron2 and a gate density of 3650 kGate/mm2, according to the paper.

At various times, IBM and its technology partners have talked about their 32-nm process with high-k and metal gates. IBM's partners include AMD, Chartered, Freescale, Infineon, Samsung, ST and Toshiba.

Moving beyond the planar transistor, IBM, AMD, Freescale and Toshiba will present a FinFET with high-k and metal gates for the 32-nm node and beyond. An SRAM cell was devised at areas down to 0.128-micron2, which is said to be the world's smallest FinFET cell to date, according to the paper.

Using 22-nm design rules, the cell was fabricated using a CMOS process flow and e-beam lithography. The cell was also devised using ''off-center design contacts and L-shaped bars,'' according to the paper.

In the cell, fin pitch was 80-nm, gate pitch and Lg were 110-nm and 30-nm. To enable high-k and metal gates, CVD-based HfO2, PVD TiN and polysilicon were deposited on the Fin portion of the device.




2. Flash memory at the 'crossroads'

SAN FRANCISCO -- At the International Electron Devices Meeting (IEDM) here, an industry expert warned that today's flash memory technology is reaching its scaling limits, thereby creating the need for the long-awaited ''universal memory'' type.

It's still unclear which technology will win the ''universal memory'' sweepstakes. 3D devices, cross-point memory, MRAM, phase-change, programmable metallization cell (PCM), resistive RAM (RRAM) and other emerging technologies are vying for acceptance in the market. Some of these technologies are in limited production right now, but all have their drawbacks.

Still, there is a pressing need for a new memory technology. In theory, today's NAND and NOR devices can scale down to least 22-nm, said Stefan Lai, president and chief technology officer at Being Advanced Memory Corp. Inc. (Woodside, Calif.).

''You can build structures at 22-nm,'' but the problem is the loss of storage electrons at these geometries, Lai said.

''Flash memory is coming to a crossroad,'' he warned during a keynote at IEDM. ''Conventional approaches will be increasingly challenged. You don't have that many generations to go.''

In a presentation, Lai listed several ''universal memory'' technology candidates. He also commented on the advantages and disadvantages of the memory types:

--3D or thru-silicon-vias: ''You are not going to save costs.''

--3D or cross-point memory: In production by SanDisk's Matrix unit. ''Cross-point is limited by lithography.''

--MRAM. The technology ''will have its market opportunities,'' but it's ''not the lowest cost memory.''

--Phase-change memory. Technology is ''my preference. Scaling is determined by materials.''

---RRAM: There is growing ''interest,'' but no high-density array has been reported so far. Cycling is not as good as phase-change.''




3.IBM gives update on STT-based MRAM

SAN FRANCISCO -- At this week's International Electron Devices Meeting (IEDM) here, IBM Corp. will provide a sneak preview of its MRAM, based on spin torque transfer (STT) technology.

In a paper, IBM will describe the key element of a 4-Kbit test device. The element, dubbed a magnetic tunnel junction (MTJ), is a 70- x 210-nm2 device said to have 10-year data retention cycle, a breakdown-to-voltage margin over 0.5-V and a read-induced disturbance rate of 10-9.

An 8-Ohm um2 MTJ is said to show ''sufficient'' read/write margin, thermal stability and write endurance. The device is said to be free of unwanted write-induced magnetic reversal.

The technology could enable a 64-megabit device based on 90-nm design rules, according to IBM's paper. IBM builds MTJs with MgO tunnel barriers. With those design rules, a single-bit line can be as tiny as 9F2.

''For the targeted MTJ operating point at (about) 4 x 106 A/cm2, the cell size is 30F2,'' according to IBM.

Last year, IBM launched a joint research and development project with TDK Corp. to create high-density magnetic random access memories (MRAMs). The new multiyear program will aim for a 20-fold increase in the memory density of MRAMs by switching to a writing mechanism, called spin-momentum transfer, that draws less power and uses smaller bit cells.

STT-based MRAM is gaining steam in the market. Korea's Hynix Semiconductor Inc. and Japan's Renesas Technology Corp. have separately announced deals for Grandis Inc.'s technology. Japan's Toshiba Corp. and Korea's Samsung Electronics Co. Ltd. are reportedly taking a close look at Grandis' technology.

IBM, Freescale and others are reportedly devising at their own STT technologies. Most MRAMs write data by applying the magnetic field generated by a current running through a wire near a tunneling magnetoresistive (TMR) element to change the magnetization. That enables fast operation but gobbles up power.

Grandis' spin-torque transfer method uses a spin-polarized current to switch magnetic bits, a technique that is said to consume less power and enhances scalability. An STT-RAM writes data by aligning the spin direction of the electrons flowing through a TMR element.

All told, STT-RAM claims to combine the capacity and cost benefits of DRAM, the fast read and write performance of SRAM, and the non-volatility of flash.



4.Latest 32nm Process, Memory Beyond Flash, and Novel Devices - 2008 IEDM,-memory-beyond-flash,-plus-novel-devices-detailed-at-2008-IED

Date: January, 2009

New memory concepts and the latest 32nm CMOS with metal gates and high-k dielectrics were highlights of the 2008 International Electron Devices Meeting (IEDM) in San Francisco, Dec. 15-17. A wide range of innovative device technology, including 3D wafer-level integration and a nanowire battery were also presented.

Rapid improvement in memory, especially flash memory now so widely used in digital cameras, notebook PCs, and other mobile devices, was described by Stefan Lai of Being AMC (formerly with Intel) in a plenary talk. He cited work to push flash toward 32nm and beyond, including the TANOS process from Samsung that incorporates a charge-trapping layer rather than a floating gate to minimize cell-to cell coupling, thus solving short channel effect problems. Another advancement from Kinam Kim of Samsung was the hemi-cylindrical FET, where channel length extends above the planar silicon surface with the TANOS charge-trapping layer wrapping around. This will allow flash to be scaled down to sub-32nm nodes, Lai said, but at these sizes NAND flash faces a bigger challenge. Only a few hundred atoms are in the charge-trapping layer, and in a multi-layer cell (MLC) only tens of electrons separate storage layers. With leakage during cycling, these few electrons will quickly be depleted, which may be OK for some consumer uses, such as memory cards for cameras, but not for the solid-state disk (SSD) in servers, Lai pointed out.

Nevertheless, Lai expressed confidence that innovative memory advances would push beyond such barriers, like some being reported at the 2008 IEDM. He cited previous work on 3D NAND layers on a single chip by Samsung, Macronix, and Toshiba, using shared lines and making a whole stack of control gates in a single step in Toshiba’s bit-cost scaleable flash. Crosspoint memories can be stacked in 3D, but process temps must be kept within limits as each layer is added, Lai pointed out. If pushed beyond 400°C, tungsten may have to be used instead of copper lines, for example.

Lai cited work being reported by SanDisk and Toshiba at IEDM 2008 to enable what they call “super multilevel NAND flash”still using a floating gate, but with tight Vth and sheet resistance control to push this technology to 32nm and beyond.

One solution to charge retention problems is to “get away from a charge storage transistor altogether,” Lai said. Device resistance may be changed by applying an electric field or current, he pointed out. A stack-friendly all-oxide 3D RAM, or resistance RAM, was reported by M.-J. Lee et. al. of Samsung, for example. It uses a GaInZnO peripheral TFT using low-temperature processing steps demonstrated by fabricating the devices on glass substrates. A specialized stacked-memory structure in a cross-point grid minimizes chip real estate.

A more exotic approach is a carbon-based resistive memory technology reported by Frans Kreupl, et al of Qimonda. The group demonstrated feasibility for resistive memory elements of graphene-like conducting and insulating carbon, as well as carbon nanotubes. This report was part of an entire session devoted to work on graphene and carbon nanotube devices.

Most likely to reach commercial production first, however, according to Lai, are phase-change memories. In a PCM device, switching current from an electrode to a chalcogenide material heats the region around the contact, which makes it amorphous or high-resistance, and quenched to make it crystalline, or low-resistance. Study of such factors as retention loss and transient effects of delay, switching, and recovery, were reported, as these devices evolve toward smaller structures and tighter pitches to make them commercially competitive.

Lai suggested that these exotic multilayer memories require repetitive processing that may need only 10-15 process tools, so this might be done in a minimal fab while the layer of complex circuitry for drivers and read sensors might be farmed out to a foundry. He also pointed out that in memory there is no such thing as “perfect data,” so new system approaches may have to evolve to deal with defects. He cited work by Systems Genetics Inc., Longmont, CO, that uses a special processor and compensation engines in a systems approach to double capacity gain and greatly boost endurance for advanced NAND devices.

The hard-disk drive (HDD) field has a larger toolbox to deal with imperfect or noisy data, and their techniques might be adapted in future multilevel memories, according to Lai.

Three-dimension (3D) chip integration using through-silicon vias (TSV) also was an important topic at IEDM, including a report on a wafer-level scheme reported by F. Liu, et. al. of IBM. It incorporates 25μm TSVs with 17:1 aspect ratio drilled by RIE with tungsten interconnects. Lock-and-key structures ensure that there is no lateral shift between wafers during a hybrid copper-adhesive bonding step.

A novel multichip module integration approach using self-assembly with defined hybrid hydrophobic areas and liquid evaporation for positioning chips was reported by T. Fukushima et. al. of Tohoku U. in Japan. It achieved about 400nm alignment accuracy.

Nanowire battery technology for next-generation electronics was reported by Yi Cui, et al, of Stanford U. Energy density for batteries has been advancing only about 8% a year thanks to packaging improvements, but this is reaching limits so new concepts are needed, Cui reported. The graphite anode in lithium batteries has very limited charge storage capacity, but higher capacity materials like silicon or germanium swell too much during alloying in bulk materials. Nanowires, however, offer an alternate approach. Studies of potential nanowire structures showed most promise for lithium inserted into silicon nanowires, but there is a problem keeping the silicon crystalline through charging cycles. The group has devised nanowire structures in which a silicon core remains crystalline under constant charging for 145 cycles with 95% charge retention, and offering about 6x the storage capacity of carbon, which shows promise for commercialization, according to Cui. The group developed a CMOS-compatible process to fabricate these silicon-lithium nanowires for on-chip power sources.

Among reports on 32nm second-generation high-k metal gate (HK+MG) CMOS logic was a late paper by S. Natarajan et. al., Intel, with enhanced channel strain, which achieves the highest drive current yet for nMOS. Another late paper by NEC reports a cost-effective approach to a 32nm CMOS platform using advanced single-exposure lithography with custom illumination to avoid the extra steps of dual exposure and double patterning. A gate-first HK+MG process was described.

Despite the weak economy, attendance for the conference remains fairly high, with over 300 attendees to the Sunday short course on 22nm CMOS technology, for example. ?B.H.