SAN JOSE, Calif. -- At next week's International Electron Devices Meeting (IEDM) in San Francisco, Calif., Intel Corp. is expected to extend its lead over AMD, IBM and other microprocessor vendors in the high-k/metal-gate race.
In a paper, Intel (Santa Clara, Calif.) will describe a new 45-nm derivative for system-on-a-chip (SOC) designs based on high-k/metal-gate technology. In addition, the chip giant will provide more details about its previously-announced, 32-nm process, based on a second-generation, high-k/metal-gate architecture. And, Intel will talk about a quantum well field effect transistor technology.
It is also working on its 22-nm technology, which is in R&D. While it did not elaborate on this technology, the company acknowledged that it may end up processing its 22-nm designs using 193-nm immersion scanners, meaning extreme ultraviolet (EUV) lithography is late to the party--again.
Regarding two other key technologies--high-k and metal-gates--a big question remains: Can Intel's competitors catch up? To date, Intel's main rival, Advanced Micro Devices Inc. (AMD), has announced its 45-nm processors, but the devices reportedly do not use a high-k/metal-gate scheme.
AMD's technology partner, IBM Corp., does not expect to have its high-k/metal-gate solution until the 32-nm node, reportedly causing some angst in the market. IBM's ''fab club'' is using a gate-first approach to high-k and metal gates, while Intel is deploying a rival replacement-gate technology.
For some time, Intel has already shipped 45-nm processors based on the technology, giving it an edge in the market. High-k and metal gates are key building blocks for scaling and reducing the leakage within the critical gate stack, enabling the next-generation transistor.
High-k uses a material called hafnium to replace the transistor's silicon dioxide gate dielectric, which is running out of gas in today's designs. Also on the transistor, a metal material replaces the polysilicon gate electrode of NMOS and PMOS structures.
Despite an endless parade of claims made by vendors, high-k/metal-gate technology is much harder to develop than previously thought. IBM's ''fab club'' is reportedly wrestling with the technology, while the foundries will not deploy the scheme until the 32- or 28-nm nodes.
With the exception of Intel, ''nobody else is shipping high-k yet,'' said Mark Bohr, Intel senior fellow and director of process architecture and integration. ''We have more than a one generation lead in technology,'' Bohr told EE Times.
At IEDM, Intel will present several papers on the subject, including at 32-nm. As far back as late-2007, the chip giant rolled out its initial 32-nm test chip. The device has a 0.171-micron2 cell size containing more than 1.9 billion transistors.
Then, in October of 2008, the company tipped its 32-nm process. As reported, the process incorporates copper interconnects, a second-generation high-k/metal-gate technology and a fourth-generation strained-silicon scheme.
Intel is expected to deploy its first immersion lithography scanners at 32-nm. The 193-nm machines will be sole sourced from Nikon Corp. (Tokyo).
The transistors feature dual band-edge workfunction metal gates and high-k gate dielectrics with an equivalent oxide thickness (EOT) of 9-nm or 9 angstroms. In comparison, the company's 45-nm high-k designs have an EOT of 10-nm. The 32-nm version enables Intel to reduce transistor variability,'' Bohr said.
At 32-nm, Intel's transistor gate pitch is 112.5-nm. Intel's 32-nm logic technology provides about 70 percent linear feature size scaling and 50 percent area scaling, as compared to the company's 45-nm process. In addition, the process enables the highest drive currents reported to date for 32-nm technology.
Intel is on track for 32-nm production readiness in Q4 2009. Meanwhile, the company is also working on its 22-nm process. The technology will make use of 193-nm immersion scanners with either double-patterning or computational lithography techniques, he said. For 22-nm, EUV ''probably won't be ready,'' he said.
At IEDM, meanwhile, Intel will describe a new 45-nm process derivative for SOCs. The process is still in the lab, but it could propel a new and important business for the chip giant.
Last year, Intel created a new SOC enablement group. Intel has stated it has at least four SoCs in the works for systems outside its traditional PC markets. Tolapai is aimed at storage networks, Silverthorne at handhelds, Larabee at high-end visualization systems and Canmore at wired consumer devices.
On the process front, the 45-nm SOC technology makes use of a high-k/metal-gate scheme that has been ''optimized for low power products,'' he said.
Within the process, the PMOS/NMOS logic transistor drive currents are 0.68/1.04 mA/um, respectively, at 1.1-Volt and offstate leakage of 1 nA/um. High voltage I/O transistors with robust reliability and other SOC features, including linear resistors, MIS and MIM capacitors, varactors, inductors, vertical BJTs, precision diodes and high density OPT fuses are employed.
And not to be outdone, Intel will demonstrate for the first time a high-speed, low-power quantum well field effect transistor. The p-channel structure will be based on a 40-nm indium antimonide (InSb) material, which is said to achieve a cut-off frequency (fT) of 140-GHz at a supply voltage of 0.5 V.
Transistors made on III-V materials are being explored in research as a means to provide improved performance and low power capabilities beyond what silicon may be able to provide.