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IEDM 2009

Articles:

1.NEC tweaks CMOS device process to 200 GHz / EETimes

2.IMEC, Toshiba claim device breakthroughs / EETimes

 

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1. NEC tweaks CMOS device process to 200 GHz



 
BALTIMORE — In the research world of electron devices there are many nuances at every step of the research process which brings researchers closer to the eventual goal of integrating analog/rf and digital devices on one chip. The ideal chip would exhibit high performance and consume low power at the same time.

And so this year, as every year, at the International Electron Devices Meeting NEC researchers put another notch in their belt for fine-tuning their CMOS process yet again.

One of this year's paper by researchers from NEC Electronics' LSI Fundamental Research Laboratory describes a new partially-thickened local (PTL)-interconnect structure with an extremely low resistance, developed for a 40 nm-node low-power CMOS device, in order to boost the RF performance of the device.

CMOS device scaling improves performance of digital operation of circuits, especially for low-power applications. However, high resistances of the scaled-down thin local-interconnect and contact degrade RF/analog performances due to the parasitic effects.

Scaled-down CMOS devices need to be designed without degrading RF/analog performances. For example, the maximum oscillation frequency (fmax) is strongly affected by the gate resistance, which includes the resistances of the silicide-interconnects, the thin local-interconnects and contacts.

NEC Electronics has developed a low-k copper interconnect technology in which the insulating dielectrics are changed from high-resistive tungsten to copper. That development was reported at the 2008 IEDM.

Now with the new PTL technology specific parts of the low-k structure can be selectively thickened in three dimensions, while the other area can remain connected only with the copper plugs that exhibit low parasitic capacitance. This mixed configuration allows the coppoer plugs are applied to the logic device areas where capaciatnce reduction is strongly required, and the PTL interconnect is implemented in analog areas, such as gate-electrcodes, where resistance is essential for flexible design layout.

Thus the newly developed PTL interconnect is ideal for low-power mixed-signal CMOS chips with digital/analog functions, according to research fellow Yoshihiro Hayashi, who is on the presenting research team at IEDM here.

"We have achieved excellent RF performance suitable for next-generation wireless communications technologies such as long-term evolution (LTE) and WiMAX specification," said Hayashi.

NEC researchers have been able to boost fmax to 200 GHz while decreasing gate resistance to 17.1 ohms. This compares to last year's results of a preceeding tweak to the CMOS porcess that had a an fmax of 170 GHz and gate resistance of 22.7 ohms.

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2. IMEC, Toshiba claim device breakthroughs



 
SAN JOSE, Calif. -- At the International Electronics Devices Meeting (IEDM) in Baltimore, Md. this week, IMEC and Toshiba Corp. separately claimed new breakthroughs.

IMEC (Leuven, Belgium) presented a paper on a gallium nitride-on-silicon (GaN-on-Si) double heterostructure FET (field effect transistor) architecture for GaN-on-Si power switching devices.

High-voltage power devices are traditionally based on Si-MOSFET structures. However, for a number of applications, silicon power devices have reached the intrinsic material limits.

GaN is the best candidates to replace silicon power devices, thanks to their high band gap properties. However, the cost of GaN power devices is high.

IMEC obtained a high-breakdown voltage of almost 1000-V combined with low on-resistance by growing an SiN/AlGaN/GaN/AlGaN double heterostructure FET structure on a silicon substrate. By combining its double heterostructure FET architecture with in-situ SiN grown in the same epitaxial sequence as the III-nitride layers, IMEC succeeded in obtaining e-mode device operation, according to the R&D group.

The resulting SiN/AlGaN/GaN/AlGaN double heterostructure FET is characterized by a high breakdown voltage of 980-V, according to IMEC.

Meanwhile, Toshiba (Tokyo) has developed a MOSFET cell, based on spin transport electronics, or spintronics. This is a technology that makes use of the spin and magnetic moment inherent in electrons.

In spintronics, electrons in a magnetic layer are spun in one of two spin states--spin up or spin down--and the majority state determines the spin state. These spin states are more or less permanent in a magnetic layer, realizing a nonvolatile characteristic that can be used to store data.

Spin current can be flowed into the same spin state in a magnetic layer, and this capability changes the impedance characteristics, which determine the read signal of a spin device.

Toshiba has introduced magnetic layers into the source and drain of a MOSFET cell, and applied these to controlling spin direction by the spin-transfer-torque-switching (STS) method, and by applying gate and source/drain voltages, according to Toshiba.

A magnetic tunnel junction is applied for write operation of STS in the magnetic layers, which are formed with full-Heusler alloy, an intermetallic that acts as a high spin polarizer.

This in turn opens the way to next-generation non-volatile semiconductor devices that can be used as reconfigurable logic devices, and non-volatile LSI chip with memory function. This work was partly supported by the New Energy and Industrial Technology Development Organization (NEDO) in Japan.

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