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IEDM 2009


1.Dissent Builds on Gate First High-k /Semiconductor International

2.Bulk Silicon CMOS May Prevail Despite Power FearsBulk Silicon CMOS May Prevail Despite Power Fears /Semiconductor International

3. Intel Takes 32 nm PMOS to Record Levels /Semiconductor International

4. Leading-Edge Logic Processes Presented at IEDM Session /Semiconductor International



1. Dissent Builds on Gate First High-k

By David Lammers, News Editor -- Semiconductor International, December 9, 2009

Problems with the gate-first approach to high-k/metal gate deposition may force IBM to switch to the gate-last approach pioneered by Intel, technologists said this week at the International Electron Devices Meeting (IEDM) in Baltimore. GlobalFoundries and other members of the Fishkill Alliance are putting pressure on IBM to reconsider its gate-first approach, which technologists said has problems with yields, threshold voltage stability, and mobilities.


Concerns about threshold voltage shifts and other performance problems with the gate-first approach to high-k/metal gate creation may cause GlobalFoundries (Sunnyvale, Calif.) and other members of the IBM-led Fishkill Alliance to shift to a gate-last technique, sources said at the International Electron Devices Meeting (IEDM), going on this week in Baltimore.

"My understanding is that the subsequent thermal steps are causing problems with the gate-first approach," said a senior vice president at Qualcomm Corp. (San Diego) who was attending IEDM. "GlobalFoundries seeks a gate-last approach, and if necessary they could drop in a gate-last module independent of IBM," the Qualcomm executive said.

Asked about the potential switch, a senior IBM technology manager said continuance of the gate-first approach after the current 32/28 nm generation is under review. Any shift to a gate-last approach, if it occurs, would come at the 22 nm node or later. "Both of the gate formation approaches have their problems, and there is no doubt that the gate-first approach is significantly simpler," he said, asking not to be identified. "For IBM, gate first will work well at the 32 nm generation, and I would not underestimate the power of incumbency, which could take it to the next (22 nm) generation. After that, we'll have to see what happens."

At IEDM, a knowledgeable source said GlobalFoundries and nearly all the other members of the Fishkill Alliance will force a shift by IBM to the gate-last approach at the 22 nm node. GlobalFoundries is mulling a switch even earlier, at the 28 nm node coming to market in about a year, he added.

Mukesh Khare, high-k program manager at IBM, said IBM "understands the fundamentals of high-k very well." He said the gate-first approach provides fewer design rule restrictions, and is simpler to implement, than the gate-last approach used by Intel. The IBM high-k technology is working "very well," he said, offering as proof an IBM 28 nm low-power process described Wednesday at IEDM with an industry-best equivalent oxide thickness (EOT). "Nobody has such a low EOT for a 28 nm LP process," Khare said.

Asked about a switch to a gate-last approach at the 22 nm node, Khare said, "I am surprised at that kind of talk. Every technology has challenges, which is why we continue to work at it and develop solutions. We take it one node at a time." He added, "At this point, no one knows what will happen at the 15 nm node. It could be finFETs that come in by that time." The fully depleted, extremely thin SOI (FD-ETSOI) approach that IBM is pursuing would provide greater electrostatic control, and take some of the burden off of the oxide layer.

A Toshiba technologist assigned to the Fishkill Alliance said the gate-last approach delivers a lower threshold voltage and higher mobilities, particularly on the PMOS transistor. Channel strain is induced when the dummy gates are removed, providing another significant increase in performance.

At the 45 nm node, when Intel introduced its gate-last process flow, the argument was that the gate-last approach required more restricted design rules (RDRs), the Toshiba manager said. Intel was able to restrict the layout of its poly gate lines to one dimension because of its in-house coordination of the process and the design rules. For foundries, the argument went, too many RDRs would inhibit fabless companies from porting chips from a SiON/poly process to a high-k process.

High-k/metal gate technology (120909HighK.jpg)

High-k/metal gate technology offers higher performance at reduced gate leakage.

However, the so-called 1-D (gates aligned only in the X or Y direction) design approach is now mainstream, and is required at the 28 and 22 nm nodes because of lithography constraints. Using a dipole illumination scheme and a 2-D poly layout approach is not practical at the leading-edge nodes, requiring leading-edge fabless companies such as Qualcomm to adopt a 1-D approach. That alignment of RDRs, lithography constraints and the performance advantages of the gate-last approach to high-k/metal is causing foundries such as Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) or GlobalFoundries to support a gate-last approach, the source said.

"As long as the designers get the electrical specs and the SPICE models, they don't care if it is gate first or gate last if the design rule restrictions are the same anyway," he explained.

Intel developed a gate-last approach, announcing it in December 2006 for its 45 nm technology. In that iteration, the hafnium dielectric was deposited by atomic layer deposition (ALD), and a sacrificial polysilicon gate was created. After the high-temperature S-D and silicide annealing cycles, the dummy gate was removed and metal gate electrodes were deposited last.

In the second-generation 32 nm gate-last approach, Intel deposits both the dielectric and the metal electrodes last, further avoiding thermal stress to the gate stack. The Intel approach requires careful control of the etching and CMP steps, among others, but delivers a better work function on the PMOS device in particular. "We have it working, as demonstrated by our 22 nm SRAM announcement a few months ago," said Mark Bohr, a senior fellow at Intel.

Intel described a second generation gate last approach to high-k deposition (120909gatelastIntel.jpg)

At IEDM, Intel described a second-generation gate-last approach to high-k deposition.

The gate-first approach was developed by Sematech and the IBM-led Fishkill Alliance. It relies on very thin capping layers — Al2O3 for the PMOS and LaOx for the NMOS transistors — to create dipoles that set the threshold voltage of the device.

In a session on high-k challenges at IEDM, Thomas Hoffmann, manager in the CMOS platform technology group at IMEC (Leuven, Belgium), said both the gate-first and gate-last process flows have delivered a resumption in scaling for the oxide inversion thickness (Tinv). "Back in the days of polysilicon (gate electrodes), it was relatively simple to tune the Vt's by doping," Hoffmann said. "With high-k, the interfaces are also electrically active, and the gate-first approach tunes the Vt by inserting capping layers."

Although the gate-first approach more closely resembled the process flow of the pre-high-k era, problems have cropped up, Hoffmann said in a Sunday short course presentation. At various technology conferences this year, researchers have discussed a rolloff of the flatband voltage, shifts in the PMOS threshold voltage, and interface layer regrowth. "When the metal sees a high thermal budget, it has an impact on the work function," Hoffmann said. Importantly, the problems created "fundamental issues for mobility, probably due to remote Coloumb scattering. It takes a fair amount of work to improve the quality of the layers to reduce these changes."

The gate-last approach gains a further performance boost from strain induced when the dummy gate is removed, he added.

Another source said the gate-first approach has yield issues. The capping layer is only ~5 Å. Defects are created from debris generated from the capping layers. Those particles impact yields "and can be the difference between profit and loss for a foundry," he said.

Veena Misra, a high-k researcher at North Carolina State University and the publicity chair of this year's IEDM, said the Vt variations seen in the gate-first approach remain somewhat of a mystery, though researchers are probing the causes. The variations could come because some of the high-temperature steps come after ALD creation of the capping layers.

"The baseline roadmap at TSMC is gate last," said Jack Sun, in charge of technology strategy at TSMC. "There is always a possibility that, based on some customer requests, that we could do a gate-first approach, though the jury is still out on that." Sun was named TSMC's CTO in November, reporting to S.Y. Chiang, senior vice president of R&D, who returned to the role recently.

However, several sources said trying to support both a gate-first and gate-last high-k solution would be expensive for any foundry, even for companies as large as GlobalFoundries and TSMC. That is causing "most of the members of the Fishkill Alliance to push IBM to change to a gate-last approach" at the 22 nm generation, a source said. GlobalFoundries has gone part of the way through development of a gate-last flow that may or may not be ready in time for the 28 nm high-performance node.

A GlobalFoundries manager said the company will stick with the gate first Fishkill Alliance high-k module for the 28 nm node. "After that, we will consider both options. The issue is that when you hit these dielectrics and metals with the thermal cycles, things change in ways that you can't control."



2. Bulk Silicon CMOS May Prevail Despite Power Fears

David Lammers, News Editor -- Semiconductor International, 12/7/2009

Speakers at an IEDM short course on scaling challenges said planar devices made in bulk silicon CMOS are likely to continue to be the basic technology platform for the next decade, despite concerns about power consumption. While III-V and germanium channels offer high mobilities and lower operating voltages, the challenges of cost, manufacturing complexity, and finding a workable gate dielectric may prevent adoption. Scott Thompson, organizer of the short course, said one exception may be Intel, which he said is seriously considering a tri-gate transistor for the outer nodes.


While researchers are still actively pursuing alternatives to bulk silicon CMOS for beyond the 22 nm node — including III-V and germanium channels, finFETs and tri-gate devices, and fully depleted SOI — cost and complexity considerations will keep most of the industry on bulk planar CMOS, speakers said at the scaling challenges short course, which preceded the International Electron Devices Meeting (IEDM) going on in Baltimore this week.

"The jury is still out" on heterogeneous devices, which would include a III-V transistor as the nFET and a germanium device as the pFET, for example, said Scott Thompson, a professor at the University of Florida (Gainesville, Fla.) who organized the Sunday short course. Although few companies appear ready to tackle the manufacturing complexity of vertical transistors, Thompson said there is a possibility that Intel Corp. (Santa Clara, Calif.) will adopt a tri-gate structure, with a less onerous aspect ratio than a finFET and the advantage of better control over the channel.

An increasing number of events are being organized around the IEDM conference. About 1200 are expected to attend the full conference, which starts today and ends Wednesday. About 600 attended the two Sunday short courses on scaling and low-power devices. Sematach (Austin, Texas), Aixtron AG (Herzogenrath, Germany) and Tokyo Electron Ltd. (TEL, Tokyo) co-sponsored an invitation-only event Dec. 5-6 on emerging technologies, including heterogeneous logic, emerging memories and energy-efficient technologies. About 165 attended the Sematech seminar. Smaller events are being organized by Applied Materials Inc. on memory technology, by ASM International on high-k dielectrics, and by Chipworks on its latest reverse engineering discoveries.

Raj Jammy, in charge of Sematech's front-end program, said high-performance devices face power restrictions that define the challenge. "We need true high-performance devices with low power too. There is a blending or convergence going on."

Heterogeneous devices are a major research theme at Sematech, IMEC and other research centers. Although III-V transistors have much higher mobilities than silicon, they are prone to leakage problems. "The challenge is how to bring out the performance without sacrificing on leakage," Jammy said. "We have to be very careful in selecting which devices would go into III-Vs, using quantum wells. And we would build those on a silicon wafer, which would be covered with an epitaxial layer of germanium so that everything runs cooler." Jammy added that the III-V devices operate comfortably at 0.5 V, providing an energy-saving opportunity.

Future heterogeneous CMOS options (120709Future-CMOS.jpg)

Future heterogeneous CMOS options include an nFET based on III-V channel optimized for electron transport properties, and a pFET based on Ge or III-Sb channel for hole transport. (Source: Sematech)


Thompson, who earlier worked at Intel before moving to Florida, applauded the research work at Sematech and elsewhere, saying heterogeneous devices are exactly the kind of investigation that should go on at consortia and universities. But he expressed doubt that enough resources are going into the myriad challenges, with a III-V high-k dielectric as the biggest. And because strain techniques and high-k/metal gate technologies are boosting bulk silicon performance for the foreseeable future, Thompson said he believes mainstream companies will avoid the additional complexity of non-planar, non-silicon devices.

Ghavam Shahidi, an IBM fellow and director of silicon technology at the T.J. Watson Research Center, was the opening speaker at the Sunday short course, providing an hour-long overview of the many technology challenges facing CMOS at 22 nm and beyond. Shahidi earlier in his career was a driving force behind IBM's 1998 decision to use SOI technology for its microprocessors, and he said, "My personal preference continues to be for SOI." But for cost-sensitive products, Shahidi said he believes most companies will remain in the bulk silicon camp.

critical thickness of the active silicon layer is a major challenge in fully depleted SOI (120709ThinSOI.jpg)

Controlling the critical thickness of the active silicon layer is a major challenge in fully depleted SOI. (Source: IBM Research)

"I'm biased toward SOI," Shahidi said, "but the jury's still out on whether SOI will see wide adoption. The starting wafer cost is one issue; it is too much for some companies." As for InGaAs and heterogeneous technologies, Shahidi said, "They are not at all ready. The gate dielectric is not there yet. The PMOS device is not ready at all. It is too late, and the silicon bar keeps going up. The III-V guys would definitely argue against that, but in my opinion silicon is cheaper, and if you can do what you need to do in silicon, why wouldn't you?"





3. Intel Takes 32 nm PMOS to Record Levels

David Lammers, News Editor -- Semiconductor International, 12/10/2009

At IEDM, Intel manager Paul Packan said Intel's flagship 32 nm technology achieved record drive current levels, with the PMOS transistor showing a 35% drive current improvement over the 45 nm PMOS device. "For the first time, linear drive currents on the PMOS have overtaken NMOS," he said. The sharp gain in PMOS performance comes partly by adding germanium to the SiGe stressors, and from the replacement-gate process.

Intel Corp. presented details on its 32 nm logic technology at the International Electron Devices Meeting (IEDM), reporting that its fourth-generation strain techniques have boosted the PMOS performance to a historic point. "For the first time, linear drive currents on the PMOS have overtaken NMOS," said Paul Packan, 32 and 15 nm technology programs manager.

For the oft-quoted saturated drive current, the 32 nm NMOS value remains higher, at 1.62 mA/μm Idsat compared with 1.37 mA/μm for the 32 nm PMOS transistor. Packan said the PMOS linear drive current (ldlin) reached 0.24 mA/μm, a 35% improvement over the 45 nm PMOS transistor. The NMOS device Idlin gained a 20% improvement, partly from a raised source-drain architecture, reaching a linear drive current of 0.231 mA/μm. Linear drive current is important because transistors rarely get to full saturation, making Idlin a meaningful metric for real-world device operation.

Intel used a raised source-drain for its 32 nm NMOS transistors (121009Intel32transistors.jpg)

Intel used a raised source-drain for its 32 nm NMOS transistors.

With NMOS and PMOS now in rough parity, designers can adjust the size of the PMOS transistors to their needs, said Mark Bohr, a senior fellow at Intel. "For many generations, there was a 2:1 ratio between the NMOS and PMOS," largely caused by inherently different mobilities between electrons and holes. "At the 32 nm generation, our saturation and linear drive currents are closer to being matched; we are getting very close." That means for the Westmere processor Intel designers could create circuits with smaller PMOS transistors in some cases, Bohr said.

The sharp gain in PMOS performance comes partly by adding more germanium to the SiGe stressors, to a 40% level. Also, "we are moving the SiGe closer to the channel at the 32 nm generation, which is challenging at these dimensions," Bohr said.

 The replacement gate technique adds another boost, rivaling that of the SiGe stressors. Before high-k/metal gate technology was introduced, the polysilicon electrode was neutral in terms of strain on the PMOS channel. With the replacement gate, or gate-last, technology, removal of the sacrificial gate allows the SiGe stress regions to exert a stronger tensile strain on the channel, reaching 2 GPa.

For the NMOS, the raised source and drain reduces resistance, "helping to mitigate the pitch scaling issues," Packan said. By moving transistors closer together, there is less room for stress regions. Though in previous interviews Bohr has not been positive about the value of SiC stressors on the NMOS channel, he declined to comment on whether Intel is using SiC at the 32 nm node.

Although Intel remains on a Moore's Law pace in terms of contacted gate pitch scaling, with a 112.5 nm pitch, shrinking is no longer delivering the speed improvements seen in past generations, Packan said. With smaller dimensions, less material can be deposited to add strain. And threshold voltages have crept up slightly in recent years at the same Ioff levels.

Without increased strain, CMOS transistors would be losing performance  (121009IntelIEDM.jpg)

Without increased strain, CMOS transistors would be losing performance as the gate length scales.

"Traditional scaling is losing steam," Packan told the standing-room-only Wednesday IEDM session on leading-edge CMOS. He estimated that were it not for the additional benefits of higher strain, performance actually would have declined for the 32 nm transistors. One reason, Bohr said, is that to counter short channel effects in the aggressively scaled gates the channel must receive higher dopant levels, causing threshold voltages to rise and slowing down the transistor.

"We need a new paradigm for performance improvement," Packan said.

Though several participants at IEDM said CMOS scaling is likely to slow to a three-year pace, Bohr said Intel plans to stay on a two-year cadence. The Westmere processors are shipping now from two Intel fabs to computer vendors, and the 22 nm technology is on pace to ship two years later. Not only does Intel want to remain ahead of its MPU competition, its computer customers need faster MPUs every two years so they can sell new systems to their customers, he said.





4. Leading-Edge Logic Processes Presented at IEDM Session

David Lammers, News Editor -- Semiconductor International, 12/18/2008

AMD, IBM and its Fishkill Alliance partners, Intel, an NEC-Toshiba collaborative effort and TSMC all presented leading-edge logic processes at 45, 32 and 22 nm design rules at the International Electron Devices Meeting (IEDM). Although several of the processes are not expected to go into production in the form presented this week, Intel said during a late paper presentation that it has completed the process development phase of its 32 nm process.

An all-star cast of companies presented leading-edge processes yesterday at a session on advanced CMOS logic at the International Electron Devices Meeting (IEDM) in San Francisco.

A presentation on 22 nm technology from a team based at Albany NanoTech (Albany, N.Y.) — including Advanced Micro Devices Inc. (AMD, Sunnyvale, Calif.), IBM Research (Yorktown Heights, N.Y.) and Freescale Semiconductor Inc. (Austin, Texas) — detailed the challenges facing leading-edge CMOS.

In the session’s opening presentation on a 22 nm SRAM, IBM researcher B.S. Haran said for 22 nm logic “there is no space left. It is such a tight pitch, it is difficult to find a place to land the contact, and a thick spacer is no longer a luxury we can afford. The spacer, gate length and contact all must be scaled.”

IBM used a double exposure/double etch process to scale the contacts.

To scale the contact pitch to 26 nm, IBM used a split mask approach with double exposure/double etch (DE2) steps. The 0.1 µm2 SRAM bit cell measures 0.554 µm (H) and 0.18 µm (W), with a contact that scales from 70 nm at the top to 26 nm at the bottom. “Getting down to the right CDs at the bottom of the contacts involved using aggressive chemical shrinks,” Haran said, combining etch steps with the use of immersion patterning.

Although printing the contacts was a major challenge, the team also faced hurdles in creating the small vias. “If we used conventional tungsten, it would be full of voids, so we used copper,” Haran said. “There are two concerns with copper vias: People are very concerned about poisoning from copper, and because the back end is near its limits for PVD copper, we had to use advanced liners to get a void-free film.”

Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) described its 32 nm technology, aimed at what R&D manager Carlos Diaz said was “high performance at low-power” applications.

Diaz opened his presentation by saying that, although TSMC could have introduced a high-k/metal gate technology at 32 nm, it decided to use high-k at the 28 nm node instead for customers needing it. The 32 nm IEDM presentation included a high-k/metal gate module with a 0.9 nm effective oxide thickness (EOT), but that technology will see production only at 28 nm design rules.

“The gate-first metal gate/high-k technology enabled us to scale the transistor; it allowed us to eliminate gate length,” Diaz said. The transistor has a 30 nm physical gate length and a 130 nm gate pitch. He said the drive currents of 1340/940 µA/µm at an off current of 100 nA/µm “are the highest drive currents reported for a gate-first process.” That was an apparent dig at IBM, which also uses a gate-first high-k/metal gate process.

During the question-and-answer session, Diaz said significant improvements to line edge roughness (LER) in the patterning steps allowed TSMC to reduce transistor mismatch, or threshold voltage variability.

Franck Arnaud, an STMicroelectronics manager assigned to the IBM Fishkill Alliance, described a 32 nm bulk technology that he said was aimed at networking, graphics and PC peripherals that require high data rates. He said the goal was to develop “the simplest, most cost-effective process possible that could be scaled to 28 nm quickly.”

The general-purpose process builds on a low-power 32 nm transistor, adding embedded SiGe to the PMOS transistor to boost the drive current to 1050/650 µA/µm at an off current of 10 nA, which Arnaud said was “a dramatic drive current improvement with respect to published foundry data using SiON” as the gate dielectric.

Intel Corp. (Santa Clara, Calif.) presented its 45 nm system-on-a-chip (SoC) process, a new flow that includes support for analog, RF and other functions needed for communications-capable devices. Chia-Hong Jan, SoC process development manager at Intel, said the defining goal for the 45 nm SoC process was to build on Intel’s processor-centric 45 nm technology and reduce the leakage current by 100×, achieving a 1 nA/ µm goal. The addition of high-k/metal gate at the 45 nm generation allowed Intel to achieve a 60% performance improvement compared with Intel’s 65 nm low-power transistor, Jan said, adding that high-k reduced the poly depletion seen at 65 nm and allowed improved stress components.

Kirklen Henson presented an IBM paper on a silicon-on-insulator (SOI) process at 45 nm design rules with a gate-first high-k/metal gate flow. After the presentation, Henson said IBM will not put the 45 nm high-k process into production, but will accelerate introduction of the 32 nm SOI process, expected to come next year.

“At the end of the day, we were striving for high drive currents at a fixed Ioff. We could get higher drive currents with scaled gate lengths, but you certainly don’t want higher power,” he said. IBM achieved a 25 nm gate length with “very nice control of short channel effects,” he said, adding that the industry is “up against a wall. We must control short channel effects, but if you are not careful you can scale the gate length and lose control of the channel.”

The technology delivered a 25% performance improvement, which Henson said was a combination of drive current measurements, ring oscillator speeds and other metrics.

Jan Hoentschel, representing a team based at AMD Dresden, described an asymmetric transistor, which alters the doping profile by tilting the implant steps, creating asymmetric halos and a steeper junction profile. The approach requires four additional mask steps and care must be taken to avoid implant blocking.

Hoentschel said the approach delivered 9-12% product-level speed improvements, and a 12% ring oscillator boost. At the post-session author interview period, he said it remains undecided whether AMD product groups will use the process.

A combined NEC-Toshiba team presented two papers — one on a 40 nm low-power CMOS, and another on a 32 nm project that incorporated a hafnium-doped gate dielectric. However, Toshiba is a member of the IBM Fishkill Alliance, and NEC joined the IBM-led alliance several months ago, making it unclear if the jointly developed NEC-Toshiba technology will ever be brought into fabs. Shunsuke Hasegawa, the Toshiba engineer who presented the 32 nm paper, said Toshiba is committed to using the Fishkill-developed process at its logic fabs. When asked about the NEC-Toshiba processes, he said the companies are still discussing the matter.

A Toshiba spokesman said the joint NEC-Toshiba process “is still in the integration stage and we have not decided, as yet, if this solution is to be applied to mass production or not, though it is one of the candidates.”

The final late paper in the session came from Intel 32 nm program manager Sanjay Natarajan, who said the 32 nm process achieves a doubling in SRAM density, with 4.2 Mb/mm2 achieved for the 32 nm technology. “This 2× density keeps Intel on the trend line for four generations,” scaling the linear dimensions by 0.7× every two years.

He rebuffed critics who have argued that high-k/metal gate steps are expensive and detract from yields. Intel claims that high-k/metal gate added 4% to process costs at the 45 nm node, and Natarajan said an additional 4% came at the 32 nm generation, which he said “is well justified by keeping Intel as the performance leader.”

The 32 nm process does not add any mask steps, and the saturated drive currents are 14% higher than the 45 nm process, Natarajan said. If linear drive currents and saturated drive currents are combined as a single metric, the 32 nm transistor is 20% faster than the Intel 45 nm transistor. “Intel has completed the development phase” of the 32 nm program, Natarajan said.