2010 IEDM Update

1. IEDM keynotes: Si's future, power's potential, bioelectronics breakthroughs

by Michael A. Fury, Techcet Group

December 8, 2010 - The 2010 IEEE International Electron Devices Meeting (IEDM) opened on Monday, December 06 at the San Francisco Hilton with a record attendance of 1645. The makeup of the submitted paper pool is shifting, with industry submissions down by 50%, university submissions up, and government submissions holding steady. This likely correlates to the industry consolidation that has taken place over the past decade, with leading edge R&D being conducted by far fewer companies now, and with greater reliance on university and consortium collaborations. However, the percentage of papers selected for presentation in the meeting remains equivalent at 48% for both industry and academia.

The president of Samsung's SAIT, Kinam Kim, gave the first of three keynote presentations, his on the challenges and opportunities for future silicon technology. He believes that DRAM will be extended to 10nm, and that 20nm NAND flash is ready for volume production now. 3D NAND is extendible to <10nm with existing technology by 2013-2015. Given the increasing aspect ratio of gate stacks, supercritical CO2 is once again evoked as a critical enabling step. Beyond NAND flash, he believes ReRAM will prove to be the best choice for both current NAND applications and for universal memory. We will have off-chip optical interconnects by 2015.

Energy efficiency enabled by power electronics was the keynote topic of Arunjai Mittal of Infineon. Windmills intrinsically generate AC current, which can be transported well enough by conventional separated AC transmission lines on land. Wind farms at sea require coaxial transmission lines to land, which generate 30% transmission losses with AC. Large rectifier systems have been developed to consolidate the wind farm power, convert it to DC for transmission to land, and reconvert it to AC for the grid, with a net loss of 15.5%. Braking systems on trains in the EU are designed to generate electricity and recapture some of that energy. Taken together, EU train braking generates 30GW/year. Lighting accounts for 20% of global energy consumption, and fluorescents are still the best value in terms of lumens per watt. New digital circuitry is being implemented in fluorescents to adjust their power usage to compensate for chemical degradation effects as the bulbs age. The electricity consumption of IT data centers exceeds the total usage of many small countries, such as Belgium and Holland. A typical data center power bill is in the range of $1.5M per month. Per month! Most of this is for air conditioning, and Infineon and others are looking at ways to reduce this energy consumption as well.

In a significant break with the past, the final keynote was delivered by Luke Lee of UC Berkeley, speaking on bio-nano science and technology for innovative medicine. A keynote on the crossover of electronics and biotechnology signifies a certain coming of age for this field, which had been growing slowly but quietly for the past few decades. Luke spoke of satellite nanoscopes, invoking the telescopes of Galileo which opened the heavens for exploration (although he originally invented the telescope to improve commerce in Venice by identifying at a distance the ships approaching port; stargazing came later). The current research has produced nanocrescent optical antenna devices, which are hollow gold spheres with an open end that can be tuned to resonate when different frequencies of light are shown on them, thus service as biological markers when they are chemically treated and attached to specific sites. In other work, he has developed a silicone microfluidic device capable of capturing and individual live cell and measuring its ionic current response to various chemicals and pharmaceuticals. This opens the door to more comprehensive testing on fully functional cells.

In my next entry, I will begin my comments on the submitted presentations and other aspects of the meeting.

On Sunday, December 05 before the technical conference officially got underway, a full day of short courses attracted 580 attendees to two separate tracks. Guido Groesenken of IMEC organized one track under the topical heading of "Reliability and yield of advanced integrated technologies." The five presentation units were:

FEOL Reliability: BTI and TDDB in high-k/metal gate, FinFET and Ge-based technologies; Ben Kaczer, IMEC.

BEOL Reliability: metal migration, stress voiding, via and low-k dielectric reliability; Shinichi Ogawa, AIST.

Electrostatic discharge aspects of FinFETs and other most advanced CMOS technologies; Christian Russ, Infineon.

Reliability-aware design of integrated circuits; Muhammad Alam, Purdue.

Yield, yield models and design for manufacturability; Andrzej Strojwas, Carnegie Mellon & PDF Solutions.

The other track, organized by Kelin Kuhn of Intel, focused on "15nm CMOS Technology," and also comprised five units:

CMOS technologies -- trends, scaling and issues; Thomas Skotnicki, ST Microelectronics.

15nm device challenges and solutions; Mukesh Khare, IBM Research.

Lithography for 15nm technology node; Sam Sivakumar, Intel.

BEOL technology toward the 15nm technology node; Yoshihiro Hayashi, Renesas.

Device / circuit interactions at 15nm technology node; Clive Bittlestone, TI.

Michael A. Fury, Ph.D, is senior technology analyst at Techcet Group, LLC

2. Dopant solutions target cost-effective semiconductor miniaturization: SRC and Waseda U. at IEDM

(December 13, 2010) -- At the 2010 IEEE IEDM conference (12/6/10, San Francisco), Semiconductor Research Corporation (SRC) and researchers from Waseda University in Tokyo announced the development of the process and materials for precisely controlling both the amount and the position of channel dopants. The researchers say this advance should help extend the manufacturability of semiconductors beyond conventional doped-channel device technologies. The result is projected to enable near atomic-scale devices and single-dopant devices.

The paper, #26.5 ("Reliable single atom doping and discrete dopant effects on transistor performance") was co-authored by NTT Basic Research Laboratories and Tohoku University, and was presented by Waseda University. According to Dan Herr, SRC director of Nanomanufacturing Sciences, "Deterministic doping, per our single-ion implantation, is a key step for the extensibility of existing doped-channel CMOS devices at 16nm and beyond."

According to SRC, the findings demonstrate the impact of a very small number of dopant atoms on device performance, making the assumption of uniform dopant distribution incorrect. The naturally occurring non-uniform distribution causes significant variability in transistor characteristics, threatening further semiconductor miniaturization.

SRC’s EVP, Steve Hillenius, told ElectroIQ’s Debra Vogler, senior technical editor, that the research allows for a tool that enables precise doping profiles -- literally putting individual atoms in a transistor channel. "As an analytical tool, it’s very useful in being able to make precise doping profiles and then studying the effects in moving one atom from one position to another in comparison with devices made with one distribution of dopants vs. another," said Hillenius (Figure). "Non-uniform doping across the channel is always a useful tool or knob to turn when designing transistors." He explained that by getting down to single ion doping, the researchers were able to do an extensive study of quantifying the effects on device characteristics depending on whether dopants were closer to the source, and then when they were closer to the drain. The researchers reported that the sub-threshold current is sensitive to the individual dopant location, and the sub-threshold current is always larger when the dopants are located at the drain side rather than at the source side.

Figure. Evaluation of electrical transport in FETS with discrete dopants.

"This research enables a real understanding of what the impacts are of process variations and very precise processing that will allow these effects to be done on a large scale," Hillenius told ElectroIQ. By doing so, the researchers are enabling device designers of processes for mass production to target a certain dopant profile to get the maximum performance out of a transistor.

Regarding its collaboration activities, Hillenius said that SRC is very happy with its collaboration and the high quality of research coming out of Waseda as well as with other universities around the world. "It’s only been the last few years that we’ve been funding research in Japan," said Hillenius. “This kind of research, in conjunction with the interests of our Japanese members, allow the university research and the students coming out to be very well suited to working in SRC member companies.”

With its Energy Research Initiative, SRC is also expanding research activities in the areas of energy and renewable energy applications. "We have a lot of hope of expanding such research in Japan," said Hillenius. The majority of members of this initiative are from countries other than the U.S. -- only two U.S. companies are involved.

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3. Inside Renesas' eDRAM structure

by Debra Vogler, senior technical editor

December 17, 2010 - At the IEDM 2010 conference (San Francisco, 12/6-12/8), at Renesas Electronics Corp. presented a paper (#33.3, "A novel cylinder-type MIM capacitor in porous low-k film (CAPL) for embedded DRAM with advanced CMOS logics,") in which it announced a new structure of logic IP-compatible (LIC) eDRAM for the next-generation system LSIs at the 28nm node and beyond. In a briefing at IEDM, Yoshihiro Hayashi, senior chief engineer at Renesas' LSI Research Laboratory, told SST about the details of its research.

Unlike stand-alone DRAM memory, it is very important that eDRAM be compatible with standard CMOS logic IP, which is integrated in an eDRAM chip, Hayashi explained. "Our new eDRAM technology embeds the capacitors, the data storage elements in DRAM, in the interconnect layer used for the logic circuits," he said (Fig. 1). "This makes it possible to create embedded memory that seamlessly combines the globally standardized logic circuit IP." The key concept of the development, he noted, here is a scalable logic IP compatible (LIC) eDRAM (Fig. 2).

Figure 1: Advantages of eDRAM.

Figure 2: eDRAM devices compatible with standard CMOS-logic IPs (logic IP compatible [LIC] eDRAM).

By embedding the cylindrical capacitors in the interconnect layer instead of forming a layer independent of the interconnect layer, this new technology obviates the need for the long bypass contacts that were formed between the logic area transistors and the interconnect layer. "The parasitic capacitance and parasitic resistance due to the bypass contacts is reduced, thus preventing degradation of logic circuit performance," Hayashi told SST. "As a result, it is now possible to design eDRAM at the 28nm node and beyond using IP developed for use in standard 28nm node CMOS logic." He explained that the idea of placing a cylinder capacitor into the interconnect layer itself was very simple in eliminating the long bypass contact. Because standard logic IP in 28nm node CMOS uses a porous low-k film in the interconnect layers, it was necessary to prepare a cylinder capacitor with the dielectric constant k=2.5 in the porous film.

The researchers had to overcome two challenges: 1) the cylinder in the porous low-k film had to have a steep profile to keep the capacitance large, and 2) the metal electrode for the capacitor had to be deposited directly on the porous film using chemical vapor deposition (CVD) (Fig. 3).

Figure 3: Illustration of technical challenges in LIC-eDRAM.

To tackle the first challenge, the team developed a special lateral etching process to adjust to a tapered profile (Fig. 4). "It worked well, and we were able to achieve almost a 90° steep profile of the cylinder," said Hayashi.

Figure 4: Fabrication of a steep profile cylinder.

With a conventional thermal CVD process, the gas-phase metal precursor molecules penetrate into the porous film comprised of large open pores just like a gas filter, explained Hayashi. To overcome it, the team controlled the pore size on a molecular scale, and developed a special porous film with 0.4nm diameter pores. "We call this film the 'molecular pore stack' (MPS) film, where the molecular size of water (H₂O) is 0.6nm, but the pore size is much smaller." By introducing this MPS film, the metal contamination in the porous film was "profoundly suppressed" because it was much smaller in diameter than that of the conventional porous film, which had a pore diameter of more than 1.0nm (Fig. 5).

Figure 5: Control of the pore structure.

According to Hayashi, however, these solutions were not sufficient to address the challenges that faced the researchers. "When applying the conventional thermal CVD method, the metal atoms, such as Ni, were only 0.2nm in size, which is smaller than the pore size in the MPS film," he said. "This allowed a few metal atoms to penetrate into the MPS film, so we needed additional technology to achieve zero contamination metal."

By this point in the work, the team realized that it had been focusing on the metal deposition process -- not the conventional thermal CVD, but the surface-absorption type CVD method. Namely, the metal precursor molecules, such as organic titanium, are designed to be larger than the pore size of MPS, and are absorbed on the MPS surface. The molecules absorbed on the surface then react with NH₃ gas to form conductive metal-nitride, TiN on the MPS surface (Fig. 6). "We have successfully confirmed that no metal had penetrated inside the MPS film," Hayashi told SST. "Therefore, we finally decided to utilize the molecular-level control technology for both the porous low-k film and the metal film.

Figure 6: Blocking of metal diffusion by surface-absorption-type TiN CVD on MPS.

Adopting the unique MPS film for the interconnect layer has suppressed the diffusion of metal electrode material into the porous low-k film attached to the capacitor sidewalls, according to Hayashi. The team reported that it was able to assure a lifetime of over 10 years for the porous low-k film between 50nm-spaced capacitors required for eDRAM at the 28nm node. "There is no apparent difference in both the electrical properties and the dielectric reliability that was observed between the new cylinder capacitor buried in the interconnect layer and the conventional one in SiO₂, under the interconnect layer (Fig. 7)," Hayashi said.

Figure 7: Plots showing cumulative probability vs. capacitance,

leakage current, and TDDB of the cylinder MIM capacitor.

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RMG and Associates

Insightful, timely, and accurate

Semiconductor Technology Consulting

IEDM 2010

1. IEDM keynotes: Si's future, power's potential, bioelectronics breakthroughs

2. Dopant solutions target cost-effective semiconductor miniaturization: SRC and Waseda U. at IEDM

3. Inside Renesas' eDRAM structure