ISSCC 2008 Highlights
1. Future Memory Technologies from Intel,
SanDisk, STMicroelectronics, and Toshiba
2. Wireless Front End Standards and Integrations
3. 802.11n, Wimax and Bluetooth Developments
4. Ultra-low Voltage Chip from TI / MIT team
5. TI 45-nm Process - Strained Silicon, Immersion
Lithography and Ultra-Low K Dielectrics
6. TI vs. Intel's Cell-phone Processor, and Sun vs.
Intel's Server's CPU
7. CPU Designers - Multi-Core Designs will be the Wave
of the Future
1. Future Memory
as a NOR
2. Wireless Front End Standards and Integrations
Nicolas Mokhoff /EETimes
(02/05/2008 1:49 PM
SAN FRANCISCO — The interface between the
antenna and silicon ICs in current wireless
chips is complicated by the proliferation of
standards. A panel at the International Solid
Sate Circuits Conference examined potential
solutions for integrating the interface onto an
"Filtering, switching and [the] interface to
the antenna are commonly done using passive
elements," said panel organizer Ali Hajimiri,
professor at California institute of Technology
(Pasadena, Calif.) "But the large number of
passives required to interface to a
multi-standard, single-chip radio increase the
component count and size of the radio."
Added Aarno Parssinen of Nokia: "When the set
of standards will be complemented with protocols
like DVB-H, LTE or WiMAX, the number of
frequency bands will be exhaustive. This has
created one of the most challenging environments
ever for electronics design."
Parssinen said the increased integration
level for ASICs has spurred development, but
most design challenges related to cost,
complexity and interference are in the
components between the antenna and silicon.
Successful designs require a comprehensive
approach including interference management and
optimization of components at the product level.
"The versatile utilization of spectrum calls
for a new set of technologies for enhancing
front-end integration," he said.
Front-end components are being integrated
into front- end modules (FEMs). According to
Rich Ruby, director of technologies at Avago
Technolgies, partitioning the front end has
split into two paths: "by-band" and
"by-technology" FEMs. By-band FEMS enable easy
migration of phone platforms using different
frequency bands. By-technology FEMS allow phone
manufacturers greater access to optimized
"While CMOS makes inroads into the
traditional markets owned by GaAs power
amplifiers, it is not clear if or when CMOS can
replace filters or, for that matter, resonators.
In the meantime, pressure to improve
performance, size and cost for both resonators
and filters continue," said Ruby.
As low-cost CMOS continues to consolidate
functionality from baseband to transceiver
GaAs power amplifiers and high-performance
filters will continue to evolve in terms of
power constraints, linearity and high rejection
with low insertion loss, he added.
Meanwhile, Axiom Microdevices, with its
distributed active transformer (DAT) technology
has developed a 50 ohm matched power amplifier
(PA) product in bulk CMOS without the use of a
module technology, which is now shipping in high
volume, claimed panelist Donald McClymont, vice
president of marketing at Axiom. "CMOS provides
the lowest cost path to product, assuming the
technical hurdles of implementation can be
crossed, of course," added McClymont. who thinks
the possibility of further integration of the
front end is hard but feasible.
"While integration of digital baseband and
radio seemed impossible less than ten years ago,
today large systems-on-a-chips with the RF,
mixed signal and digital blocks integrated on
the same die are almost inevitable," said
Broadcom's Hooman Darabi.
3. 802.11n, Wimax and Bluetooth Developments
(02/05/2008 10:13 PM EST)
SAN FRANCISCO, Calif. — The cost of the latest Wi-Fi and
Bluetooth links are headed south, and WiMax may come
cellphone near you soon. Those were some of the
conclusions from an afternoon session on wireless
networks at the International Solid State Circuits
Conference here Tuesday (Feb. 5).
Communications hit a twofer with integrated
802.11n and Bluetooth devices described at ISSCC. In
other wireless developments, STMicroelectronics
disclosed early work toward bringing Wi-Fi and WiMax
into the cellphone.
"We are very proud of the die size of this chip,"
said Masoud Zagari, director of
analog engineering at Atheros who delivered a paper
on an integrated .11n chip.
Zagari claimed the paper was the first published
report of a .11n
chip with integrated radio and baseband, although
other vendors are preparing similar parts, he said. The
130nm device measures just 32 mm-squared.
The chip, expected to ship soon, implements a 2x2
architecture and delivers throughput of about 205
Mbits/second. Eventually, vendors will be able to craft
four-channel .11n parts that hit data rates up to 600
Mbits/second, he said.
More integration is also part of the road map for
next-generation Wi-Fi chips, as low-noise amplifiers,
power amplifiers and harmonic filters move on chip
Separately, Atheros also delivered a paper on an
integrated Bluetooth 2.1 chip. Its die size is
9.2mm-squared, shaving a square millimeter off the
smallest chips announced by Broadcom Corp. at last
"We picked analog architectures for the smallest die
area," said Dave Weber, an analog design manager who
presented the paper. "A few pennies are the difference
that makes your profit margin in Bluetooth these days,"
For its part, STM described early research prototypes
on the road to creating a single chip that will bring
.11n and WiMax into a cellphone. In separate papers, STM
described transmitter and receiver blocks that handle
both networks in the 2.4
The company is just two weeks away from taping out a
follow-on research prototype chip that puts the Wi-Fi/WiMax
transceiver and synthesizer on a single die. All the
parts are on a 65nm process, but commercial versions may
be in a finer geometry.
The separate receiver, transmitter and synthesizer
blocks now dissipate about 270 mW total. But that will
fall as the blocks are brought on to a single die and go
through a process shrink, said Andras Pozsgay, an RF R&D
project leader at STM.
The chip delivers data rates up to a Mbit/s over a 10
MHz WiMax band. It could also be tailored to handle
the LTE next-generation cellular standard since both LTE
and WiMax use OFDM technology.
"There are a lot of cellular companies interested in
WiMax these days including Motorola and Sprint," Pozsgay
4. Ultra-low Voltage Chip from TI, MIT
Colin Johnson /EETimes
(02/05/2008 10:01 AM EST)
PORTLAND, Ore. — Texas Instruments claims its 16-bit
microcontroller is the world's lowest-power device, but
a new version implementing an experimental design
technique conceived at the Massachusetts Institute of
Technology promises another 10-fold cut in power
The new low-power chip design will be described
Tuesday (Feb. 5) by TI and MIT engineers at the
International Solid State Circuits Conference in San
Francisco. "These design techniques show great potential
for future low-power integrated circuits," said
Dennis Buss, chief scientist at Texas Instruments.
The design technique works by powering parts of the
chip at just 0.3 volts, or as much as 10 times less
power than normal. This was accomplished by designing
on-chip, high-efficiency DC-to-DC conversions to operate
circuitry that normally hogs current. The
system-on-a-chip solution required redesigning select
memory and logic circuits to operate at the lower
Another key to the design was overcoming processing
variations on chips, since even the slightest variations
are exaggerated by the ultra-low power operating
"A big part of our strategy was designing the chip to
minimize its vulnerability to such variations," said
Anantha Chandrakasan, team leader and a professor of
electrical engineering at MIT
TI and MIT engineers will demonstrate the new design
technique using TI's MSP430 microcontroller, but claim
it can also be used to redesign key circuitry in a wide
variety of chips. These include devices ranging from
cellphones to medical implants to wireless sensor
networks. Portable devices based on the technique could
increase battery life by a factor of 10, according to
the developers, and some could even run off of
energy harvested from the environment.
The design technique could show up "in five years,
maybe even sooner," said Chandrakasan.
Medical implants are an especially attractive
application, according to Chandrakasan, because the
ultra-low voltages could be harvested from the "ambient
energy" in a patient's body, thereby powering medical
implants indefinitely without batteries.
Portable devices could also be based on the new
design technique, according to Chandrakasan, as well as
military applications such as ultra-small wireless
sensor networks that could draw power from the
environment after deployment on the battlefield.
Research funding for the project was provided by the
Defense Advanced Research Projects Agency and Texas
5. TI 45-nm Process - Strained
Silicon, Immersion Lithography and Ultra-Low K Dielectrics
(02/05/2008 2:06 PM EST)
PORTLAND, Ore. -- The first 45-nanometer chip to be designed
by Texas Instruments, and fabricated by a foundry, uses new
processing technology never before revealed by TI. The
design details of the 45-nanometer process used to lower
power by 63 percent and increase performance by 55 percent,
compared with its 65-nanometer process, will be revealed
Tuesday (Feb. 5) by TI at the International Solid-State
Circuits Conference here.
Now that TI is sampling its first 3.5G baseband and
multimedia processor using its 45-nm process, the company
will reveal how strained silicon, immersion lithography and
ultra-low K dielectrics enabled it to double the number of
chips produced on each 45-nm silicon wafer, while
simultaneously achieving its lower power and higher
The 3.5G baseband processor is used by OEMs to create
smaller, lower profile, portable 3.5G devices, such as
mobile handsets, with advanced multimedia
functionality--including high-definition video playback,
longer video recording and multitasking--without reducing
the battery life.
According to Uming Ko, TI Senior Fellow and director of
TI's Wireless Chip Technology Center, TI's power and
performance management technology, called SmartReflex (first
introduced at the 90-nm node), has been upgraded for the
45-nm node with several proprietary technologies in addition
to strained silicon, immersion lithography and ultra-low K
TI's 45-nm process is mixed signal, allowing both analog
and digital devices to be integrated onto chips containing
hundreds of millions CMOS transistors while maintaining a
tiny footprint, enabling the 3.5G baseband processor to
measure just 12-by-12 mm in its package.
The 3.5G baseband processor is based on three components,
the ARM-11, the TMS320C55 DSP and the image signal
processor, as well as all the necessary analog components
required for mobile handsets, such as the radio-frequency (RF)
codec. The high speed of the DSP will enable 3-D games to
run using HD quality, while simultaneously permitting video
conferencing among players. OEMs will also be able make
longer HD video recordings, as well as extend both talk and
stand-by-time on battery-operated devices, according to the
company. Ko claimed that TI's low-power, high-performance
45-nm process includes adaptive, dynamic voltage adjustment
to match user demands to processor speed without the extra
wafer-processing steps to create logic transistors with
different threshold voltages, which has been necessary for
previous generation chips. TI's 45-nm process also segments
on-chip memory to lower its voltage requirements while
simultaneously expanding its size, said Ko.
Ko also previewed new power-management tools for speeding
up system-on-chip designs by automating register transfer
6. TI vs. Intel's Cell-phone
Processor, and Sun vs. Intel's Server's CPU
(02/04/2008 12:00 AM EST)
Intel Corp. will unveil the world's biggest commercial
microprocessor as well as its smallest and lowest-power X86
chip to date at the International Solid-State Circuits
Conference in San Francisco this week. But a server
chip from Sun Microsystems and a cell-phone processor
from Texas Instruments debuting at ISSCC will outflank Intel
on both fronts.
Hoping to enable a new class of PC-compatible handheld
devices, Intel will describe Silverthorne, a full X86 CPU
that can handle active work at power consumption levels as
low as 600 milliwatts. The device will eventually hit 2-GHz
clock rates at its maximum 2-watt dissipation, thanks in
part to Intel's latest 45-nanometer process technology.
Based on a new core, Silverthorne will deliver peak
performance similar to the Pentium M (aka Banias) that
powered the first-generation Intel Centrino notebooks.
"What has a lot of OEMs excited is the dynamic range of
this processor," said Justin Rattner, chief technology
officer of Intel. "It can be active at less than 1 W, but
when it has a workload in front of it--like interpreting
byte codes to render a Web page--it can really crank."
Intel tried to reduce power consumption to 2 W on its
existing Merom notebook core--a three-issue speculative
pipeline--but "found it wasn't feasible," Rattner said. A
research project dubbed Snowcone plowed a different path,
which the Austin-based Silverthorne team eventually adopted.
"We became convinced that a simpler [in-order] two-issue
core more reminiscent of the Pentium was the best approach
to get to sub-1-W power consumption," Rattner said.
The 25-mm2 chip uses a host of power
management techniques, including the ability to switch in or
out of a new C6 deep-sleep state in just 100 microseconds.
Intel redesigned its register files and
cache circuits for lower active and standby power,
created new I/O power planes and enabled the chip's
bus with an optional energy-efficient
While Silverthorne makes strides ratcheting down the
power of an X86 processor, it is still a long way from
integrated cellular chips that aim to deliver PC-like
functions to pocket-size communicators. For instance, at the
same ISSCC session, Texas Instruments will describe a
cellular chip capable of decoding MPEG-4 video streams that
includes an 840-MHz ARM11 to run applications, a 480-MHz TI
C55x DSP core to handle 2G and
baseband comms, and a 240-MHz image processor.
The chip, a custom design for a cell phone maker expected
to ship it in handsets this year, consumes 500 mW peak and
for some cell phone apps as little as 100 to 250 mW. In
deep-sleep mode, it dissipates microwatt range.
"It's all about power in this market, where we are
designing systems based on 22-gram batteries," said Jeff
Bellay, vice president of wireless advanced technology at
To reduce power, TI used independent power domains,
dynamic frequency and voltage scaling, adaptive voltage
scaling and split-rail SRAMs and ROMs. The chip is believed
to be the first 45-nm cellular processor TI has publicly
described and the first to crank an ARM11 processor to 840
By contrast, Silverthorne is part of a broader group of
five or more chips--including Wi-Fi and ultimately WiMax
silicon--that Intel will gather into designs for so-called
ultramobile PCs and mobile Internet devices.
"The competition considers 2 watts laughable," said Will
Strauss, principal of Forward Concepts (Tempe, Ariz.),
referring to Silverthorne's maximum dissipation. "Six
hundred milliwatts is the power budget for an entire cell
phone processor and baseband."
Intel is not aiming Silverthorne at smart phones,
however, but at a class of devices somewhat bigger and more
powerful, potentially running full Windows Vista software
"Silverthorne probably won't appear in anything much
smaller than a paperback book," said Nathan Brookwood,
principal of market watcher Insight64 (Saratoga, Calif.).
But a follow-on design with lower power consumption in 2009
"could very well appear in smart phones," he said.
Whether the new systems that Intel has roughly described
as ultramobile PCs and mobile Internet devices take root
remains to be seen. Analysts expect the market for smart
phones--of which the ARM-based Apple iPhone is now the
poster child--to grow from fewer than 100 million units this
year to more than 400 million units by the end of 2010.
"It's not clear if Windows makes it down into this [ultramobile]
form factor successfully," said Brookwood. "The initial
ultramobile PCs from Samsung and OQO have not set the world
Qualcomm also aims to enable very powerful yet mobile
systems with its pending Snapdragon architecture, believed
to be based on a modified version of the ARM Cortex core.
"All these companies are targeting the ultramobile
device," said Strauss.
Sun, Intel in server fray
computer servers, Intel will roll out a four-core
version of its Itanium server CPU that packs a whopping 2.05
billion transistors--more than have ever been used in a
commercial microprocessor, according to the ISSCC
organizers. Tukwilla measures in at nearly 700 mm2
and consumes an equally hefty 170 W.
Intel claims that a 130-W version of the chip will double
the performance of its current dual-core Itanium. Tukwilla
marks Intel's move into server chips that integrate a memory
controller and high-performance interconnect similar to the
Opteron server CPUs of archrival Advanced Micro Devices.
Tukwilla runs at up to 2 GHz, packs 30 Mbytes of cache
and is the first Intel CPU to support the company's new
QuickPath processor interconnect, which competes with AMD's
HyperTransport. QuickPath is slated to appear on several
Xeon server processors starting late this year.
Sun Microsystems will outshine Tukwilla with the
disclosure of its long-awaited Rock processor, a 16-core
chip running at up to 2.3 GHz that breaks fresh ground in a
number of areas. Rock is the first CPU to implement scout
threads and transactional memory--two features expected to
become increasingly important for multicore microprocessors.
Each of Rock's 16 cores supports two simultaneous
computing threads. In addition, each core supports up to two
scout threads that can not only pre-fetch and execute but
retire instructions in an out-of-order fashion without using
traditional, complex out-of-order memory structures, said
Marc Tremblay, chief technology officer of Sun's
Hardware support for the scout threads required only
about 5 percent of the nearly 400-mm2 die, in
part because the cores were already multithreaded. "We
effectively added 3-D structures where you can essentially
hide bits under wires of a multiported register file,"
With similarly small hardware additions, Rock supports
so-called atomic transactions. By tagging groups of
instructions to execute at essentially the same time, the
technique reduces the complexity and inefficiency of current
locking mechanisms used to synchronize operations,
especially in large database software.
Computer scientists have long seen the feature as one of
the initial planks of a new parallel programming model that
will be needed for multicore architectures. As the first to
implement it, however, Sun risks being ahead of broad
Tremblay said the syncing mechanism in widely used Java
code maps well to the new Rock instructions, and Sun's
Solaris operating system and thread libraries will support
atomic transactions so users can get immediate benefits. As
for third-party databases and other applications, he said,
"I believe we will have ISVs support this the day we ship
Sun is working to create a consortium that would define
an application programming interface for its implementation
of atomic transactions and make the
API available as open-source software. At least two
large computer user organizations are backing the move.
Sun is also developing a simulator for its approach that
will be released as open-source software. It is still
possible, however, that competitors such as IBM, Intel and
Microsoft could be motivated to define a competing standard
before Rock-based systems ship.
One other novel feature in Rock is an approach to linking
multiple CPUs in a system via direct memory connections over
a 2.67-Gbit/second interconnect. Tremblay would not say how
the approach works or how many CPUs can be linked, but he
did say, "There is no such thing as local CPU memory in our
One blemish on the Rock design is that it sports a peak
power consumption of 250 W. "We decided what mattered was
power efficiency [more than overall power], and it is an
air-cooled processor" that uses no exotic thermal
technologies, Tremblay said.
He would not share performance data for the processor but
said it meets its targets of having the best multithreaded
performance and "competitive" single-threaded performance.
A version 2.0 of the chip is expected to tape out in a
few weeks, Tremblay added, and systems based on it could
ramp within a year.
Without hard performance numbers, it is difficult to
gauge how Rock will fare against server chips from IBM and
Intel, said Brookwood.
Nevertheless, the analyst noted that "Rock is
implementing features other people have only talked about.
[Sun] can do that because they have a much simpler core" and
their own operating system.
Overall, Brookwood added, "Sun has gotten a lot further,
in less time, with the concept of thread parallelism it
defined in 2002 than Intel has with the instruction
parallelism it defined in the early 1990s for Itanium."
7. CPU Designers - Multi-Core
Designs will be the Wave of the Future
(02/06/2008 1:41 PM EST)
SAN JOSE, Calif. — Microprocessor engineers agree multi-core designs
will be the wave of the future, but they differ widely on how to
implement them and surmount the many challenges they pose.
That was the conclusion from an evening panel on the topic at the
International Solid State Circuits Conference here Wednesday (Feb
5). The panel gathered senior
chip designers from Advanced Micro Devices, IBM, Intel, Renesas,
Sun Microsystems and startup Tilera.
Chuck Moore, an AMD senior fellow, made the case for the shift to
a new software model based on heterogeneous collections of cores
optimized for various tasks. He suggested computers should be more
like cellphones, using a variety of specialty cores to run modular
software scheduled by a high-level applications programming
"We foresee a move from compatibility based on instruction set
architecture to compatibility based on an API," said Moore. "You
get an order of magnitude better power efficiency by going to
heterogeneous cores. Already Microsoft's DirectX APIs tackle a wide
variety of graphics processors, so this is a mature software model,"
Atsushi Hasegawa, a senior chief engineer at Renesas, generally
agreed. He suggested the cellphone's use of many specialty cores
working in concert is a good model for future multi-core designs.
Brad McCredie, a chief microprocessor engineer at IBM, took the
middle ground. He suggested
computer processors will go through a phase of experimenting
with on-chip accelerators such as the IBM Cell. But ultimately the
architectures will narrow down to using to a handful of specialty
cores placed next to many general-purpose cores.
Anant Agarwal, founder and chief executive of startup Tilera,
took the opposing view. He said multi-core chips need to be
homogenous collections of general-purpose cores to keep the software
model simple. However, he was the most aggressive of any of the
panelists in his predictions for the growth in the number of cores
socket over the coming decade.
"I would like to call it a corollary of Moore's Law that the
number of cores will double every 18 months," said Agarwal whose
company currently ships a 64-core embedded processor.
Agarwal estimated by 2017 embedded processors could sport 4,096
server CPUs might have 512 cores and desktop chips could use 128
"The question is not whether this will happen but whether we are
ready," he said
Multicore design will deliver a server farm on a chip, shrinking
the size of data centers. It could also create desktops that
automatically index personal pictures based on facial recognition
software, he added.
In Agarwal's view the industry needs to deliver a new software
model because today's
operating systems which use threads and
cache coherency snooping will not scale to such multi-core
Linux will go the way of the dinosaur," said Agarwal.
Other panelists were not as aggressive as Agarwal, generally
predicting microprocessors will have fewer cores in the next decade.
For example, Rick Hetherington, chief technologist in Sun's
microelectronics group, suggested servers may have only 32-128 cores
by 2018. That's ironic given Sun currently leads the industry in
shipping more cores per die than its competitors in computer
Hetherington also suggested today's software model will survive
through the next decade. "I think we can support 500 to 1,000
threads per core. In fact, that may even happen in the next five or
six years," he said.
Sun's multi-core strategy is based in part on handling
thread-rich workloads in the rising tide of Web based applications
for giants such as Google. The rise of virtualization in server
environments could also fuel Sun's strategy.
McCredie of IBM took issue with Sun's view, suggesting today's
servers must run a wide variety of applications, including many
"Today's data centers run a big pile of goofy apps where many
people don't even know where their source code is anymore," he said.
"Google is an exception. We still have discussions about
single-threaded apps with customers who may run these applications
forever," he added.
Shekhar Borkar, director of Intel Corp.'s Microprocessor
Technology Lab, said microprocessor cores will get increasingly
simple, but software needs to evolve more quickly than in the past
to catch up.
"A core will look like a NAND gate in the future. You won't want
to mess with it," said Borkar. "As for software, the time to market
has been long in the past, but we can't afford to let that be the
case in the future," he added.
Dave Ditzel, former CPU architect at Sun and founder of Transmeta,
agreed. A member of the audience, Ditzel told the panel he helped
design Sun's first 64-bit
CPU then waited nearly ten years before commercial
64-bit operating systems became available.
Ditzel borrowed a metaphor from Berkeley computer science
professor Dave Patterson to describe the current situation.
"With multi-core it's like we are throwing this Hail Mary pass
down the field and now we have to run down there as fast as we can
to see if we can catch it," Ditzel said.