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ISSCC 2009


1. Intel lists five challenges for IC scaling / EETimes

2. SanDisk, Toshiba tip new x3, x4 NAND / EETimes

3. Intel, NEC show diverging CPU paths/ EETimes

4. Australian startup claims RRAM breakthrough / EETimes



1. Intel lists five challenges for IC scaling

SAN FRANCISCO -- Chip scaling will continue for the next several years, but there are several challenges that face IC makers.

At the International Solid-State Circuits Conference (ISSCC) here, Mark Bohr, Intel senior fellow and director of process architecture and integration at Intel Corp. (Santa Clara, Calif.), outlined the challenges and potential solutions. Bohr listed five major stumbling blocks--or challenges--for the 32-nm node and beyond:

1. Patterning or lithography

Problem: Wavelength has been scaling at a slower rate than the IC feature size.

Current solutions: ''Resolution-enhancement techniques, such as optical-proximity correction, phase-shift masks, and immersion lithography, have been introduced to bring us to the 32-nm generation. But even with these enhancements, layout restrictions, such as unidirectional features, gridded layout and restricted line plus space combinations, have had to be gradually adopted.''

Future solutions: ''Double-patterning techniques and computational lithography are options being investigated to continue scaling to 22-nm and possibly 16-nm generations before extreme ultraviolet (EUV) lithography could be ready to provide a significant wavelength-reduction and resolution enhancement.''

2. Transistor options

Problem: Classical scaling ended in the early 2000s due to gate oxide leakage.

Current solutions: ''Strained silicon, high-k dielectrics and metal gates have been significant innovations that have allowed MOSFET density, performance and energy efficiency to show continued improvements past when traditional scaling techniques ran out of steam.''

Future solutions: ''Substrate engineering makes use of wafers to improve p-channel mobility, but may not offer any advantage for n-channel devices. Multi-gate transistors such as FinFET, Tri-Gate and Gate-All-Around devices offer improved electrostatics and steeper sub-threshold slopes, but may suffer from higher parasitic capacitance and parasitic resistance.

''III-IV channel materials such as InSb, InGaAs and InAs are showing promise for providing high switching speed at low operating voltage due to increased carrier mobility, but challenges remain before a practical CMOS solution will be ready.

3. Interconnect options

Problem: New solutions are required to slow resistivity and other problems.

Current solutions: Today's processes use copper interconnects, low-k and other technologies to enable interconnect scaling at a rate of 0.7x per every generation.

Future solutions: ''3-D chip stacking combined with through-silicon-vias provides a high density of chip-to-chip interconnects. The downside of 3-D chip stacking in this manner include the added process costs of (TSVs), the silicon area lost on the chip that has vias cut through it, and the challenges of delivering power and removing heat from the stack.

''Optical interconnects can address this bandwidth bottleneck if technologies can be developed that cost effectively integrate photonics with silicon logic. Using optical interconnects for on-chip signaling may be further off in the future due to the difficulties with scaling optical transceivers and interconnects to the dimensions required.''

4. Embedded memory

Problem: High-density memory beyond SRAM is needed in today's devices.

Current solution: Traditional 6T SRAM cells are used in processors and other products.

Future solutions: ''In additional to traditional DRAM, eDRAM and flash-memory options, floating body cell, phase-change memory and seek-and-scan probe memory options all provide greater bit density than what 6T SRAM cells can provide. But integrating a novel memory process together with a logic process on a single wafer without compromising one or the other could be difficult.''

5. System integration

Problem: It is not sufficient to take smaller transistors as they become available to simply make more complex versions of the same system components.

Current solutions: ''The new era of microprocessor scaling makes greater use of energy efficiency, power management, parallelism, adaptive circuits and SoC features to provide products that are many-core, multi-core and multi-function.''

Future solutions: ''As we ponder the best paths to take in doing higher level integration in the electronics world, we may consider examples provided by nature (such as the human brain).




2. SanDisk, Toshiba tip new x3, x4 NAND

SAN FRANCISCO -- It's a next-generation memory party at the International Solid-State Circuits Conference (ISSCC) here.

At the event, the team of SanDisk Corp. (Milpitas, Calif.) and Toshiba Corp. (Tokyo) will present papers on three-bit-per-cell (x3) and four-bit-per-cell (x4) NAND flash memory.

Previously, the companies have disclosed three-bit-per-cell NAND, based on 43-nm technology. Now, they are presenting a paper on a 32-Gb, three-bit-per-cell device, based on sub-35-nm CMOS technology.

The chip measures 9.215- x 12.247-mm2 for a total of 113-mm2, enabling the 32-Gb device to fit in a microSD memory card, according to the paper.

''The chip architecture has 2 planes with 1.4K blocks/plane, 1.5MB block size and (an) 8KB page size,'' according to the paper. ''For (three-bit-per-cell) storage, narrow distributions of 8 storage levels are needed within a limited cell threshold-voltage (VT) window.''

In a separate paper, the companies have developed a 64-Gb, four-bit-per-cell device, based on 43-nm technology.

The 5.6-MB/second device has two 32-Gb memory arrays, according to the paper. ''One NAND string is composed of 66 NAND cells,'' the paper said. ''With 64 wordlines (WL) per block, (the device has) 4 pages per WL, and an 8KB page, with (a) block size of 2MB,'' according to the paper.

Seeking to take the technology lead in NAND flash, SanDisk recently disclosed that it will roll out 32-nm devices in 2009. SanDisk's partner, Toshiba Corp., will also reportedly roll out 32-nm NAND chips in the later part of 2009.


Others are also rolling out new and leading-edge NAND devices, but the real question is if or when the overall market will recover.



3.Intel, NEC show diverging CPU paths

Stacked memory route vies with system-on-chip
SAN FRANCISCO, Calif. — Intel detailed its most highly integrated CPU to date at the International Solid State Circuits Conference (ISSCC) here Monday (Feb 9). A separate paper from NEC showed a promising approach to building processors out of stacked memory and logic chips.

The two papers raised the question of whether the future of microprocessors will be down the system-on-chip or system-in-package road. While that issue gets debated, Intel's dominance in microprocessors is increasingly apparent.

Intel supplied four of eight papers at the session where NEC's paper was the only other to generate a buzz. "It was a dry year," said Krste Asanovi, a computer science associate professor at Berkeley.

The gap between Intel and its rivals Advanced Micro Devices, IBM and Sun Microsystems is expected to widen. One rival remarked with amazement that, despite the deep recession, Intel still plans to ship 32 nm CPUs in 2009.

"We probably will not do that until 2011," said the engineer who asked not to be named.

In one of its papers Intel described Nehalem-EX, a 2.3 billion transistor server CPU, a member of its 45 nm Nehalem family expected to ship this fall. The chip includes eight cores supporting dual threading, two memory controllers and four 6.4 GigaTransfer/second point-to-point interconnects to create direct links between multiple CPUs in a high-end server.

The architecture mirrors that of archrival AMD which integrates memory controllers and the HyperTransport interconnect on its CPUs. Intel's QuickPath Interconnect (QPI) is "the biggest platform change Intel has made in 10 years," said Rajesh Kumar, an Intel architect who gave a separate paper on the Nehalem family.

Intel spent much of its time discussing its techniques for low power consumption on processors such as the Nehalem-EX which dissipates up to 130 W. The processor uses three separate voltage and clock domains to optimize control of its cores, I/O and non-core areas. It can also disable unused QPI ports in idle power to save on average about 2W per disabled port.

Nehalem also marks a shift away from fast domino circuits used for the previous CPUs to more power efficient static circuits.

"In the 1990's our focus was on performance at all costs," said Kumar. "We built circuits that were inherently faster, but they were burning a lot of power for small gains. With Nehalem we could not afford that anymore," he added.

A paper presented by Hideaki Saito, a principal researcher at NEC, suggested it's time to move to system-in-package technology for processor memory, at least for complex chips used in devices such as smart phones.

Saito described a technique for stacking a memory chip and mobile processor using direct aluminum-to-copper links. The memory chip is based on a 2-D array of SRAM cells that can be configured to link with various logic blocks based on the needs of a given application.

NEC researchers created a novel network interconnect for the stack. It also developed a unique 10-micron pitch electrode to link the two die.

The company created a prototype chip using a Mbit-class memory array fabricated in a 90 nm process and linked to a processor chip via 3,269 electrodes. The links had a 93 picosecond delay.

Saito claimed the approach would deliver fast memory access. It also lets chip makers fab memory and processor die in separate processes to save cost.

"I think it is very promising, but I would not use the reconfigurability because it would add more latency," said one processor designer who attended the session but asked not to be named.

Asanovi of Berkeley said he thought the approach would be too costly, especially if the interconnect scheme introduced yield problems. "It's just a research project," he said.

Indeed, Saito said it would be at least two years before his work might be applied to commercial product.



4.Australian startup claims RRAM breakthrough

SAN JOSE, Calif. -- Startup 4DS Inc. has emerged from stealth mode and claims to have made a major breakthrough in resistive random access memory (RRAM) technology.

4DS (Fremont, Calif.), a subsidiary of an Australian company called 4D-S Pty. Ltd., has also garnered a new round of funding and is now looking for manufacturing partners to commercialize its RRAM technology. The startup is not giving a paper at this week's International Solid-State Circuits Conference (ISSCC), but it appears to want to crash the party.

For years, chip makers have been talking about the development of RRAM, a non-volatile memory and potential ''universal memory'' that combines the density of flash memory and the speed of DRAM. But to date, RRAM technology has been stymied due to material and manufacturing challenges.

A number of companies in Europe, Japan, Korea and the U.S. are scrambling to develop RRAMs. 4DS claims to have beaten its rivals to the punch, by demonstrating RRAM cells and a process within its small-scale fab in Fremont.

The company is now looking for a manufacturing partner to bring its so-called ''4DS memory'' into mass production, said Kurt Pfluger, chief executive of 4DS. "It's a simple process,'' Pfluger said. ''This has the potential to replace DRAMs and flash.''

FRAM, MRAM, phase-change, RRAM and other technologies are vying for dominance in the ''universal memory'' race. RRAMs have been the subject of academic research since the discovery of the electrical pulse induced resistance change effect in such films around 2000.

RRAM cells are usually two-terminal devices based on perovskite-oxide thin film materials. Resistive switching memories are based on materials whose resistivity can be electrically switched between high and low conductive states. RRAM is becoming of interest for future scaled memories, because of their intrinsic scaling characteristics compared to the charge-based flash devices, and potentially small cell size, enabling dense crossbar RRAM arrays using vertical diode selecting elements.

Over the years, a slew of companies have explored RRAMS--with little or nothing to show for it. Sharp, Sony, Samsung, LSI, Panasonic, Winbond, Unity, Hynix, Micron, Elpida and others have or are exploring RRAM. In fact, Japanese chip makers have reportedly poured a combined $100 million in RRAM development, but they have failed to deliver a product.

The latest major effort is taking place in Europe. In order to explore the scaling limitations of conventional flash memory cells, European research institute IMEC has started looking at RRAM cells. Five of the leading memory makers--Samsung Electronics Co. Ltd., Hynix Semiconductor Inc., Qimonda AG, Elpida Inc. and Micron Technology Inc.--are involved in the IMEC core CMOS research program and are set to share the cost and benefit from the results of the research.

IMEC's research activities on RRAM mainly focus on investigating the switching behavior of the RRAM cell concept that uses metal oxides as a switching element, and on demonstrating its scaling capability down to 25-nm. The leading material candidate is nickel-oxide, which has been the subject of study by Samsung at geometries greater than 100-nm.

At 4DS, the startup is taking a different approach than IMEC, but it did not reveal its secret sauce. The startup was formed in 2007, after it acquired some technology from an intellectual-property (IP) house. At the time, 4DS obtained some funding from PricewaterhouseCoopers and a number of investors in Australia and other regions.

Last year, Pfluger joined the company as CEO. He has held various management positions at Apogee, In Electronics and others. Other key executives at 4DS include Dan Brors, director of engineering, and Lee Cleveland, director of product development.

Last month, 4DS received a new round of funding from Poly Plant Project Inc. (Burbank, Calif.), a designer and builder of manufacturing plants for the production of polysilicon. Tetsunori (Terry) T. Kunimune, chairman and CEO of the company, has joined 4DS' board.

Now, it is gearing up for the commercialization stage. ''4DS memory has the potential to replace all existing semiconductor memories and can be manufactured in a fraction of the process mask steps above standard CMOS as comparable memory technologies such as flas and DRAM,'' Pfluger said. ''The 4DS method uses existing semiconductor processes and requires fewer changes to the semiconductor manufacturing equipment, enabling simple manufacturing through a technology that can be scaled significantly farther than NAND or NOR flash.''

4DS' RRAM is a high-capacity, non-volatile memory with fast switching speeds measured below 5-ns, and with an endurance of 1 billion write/read cycles. Compared to flash memory, RRAM requires lower voltages and lower currents, enabling its use in low power applications, he said.

RRAM exhibits lower programming currents than phase-change memory or PRAM, the company said. Compared to MRAM, RRAM has a simpler, smaller cell structure. MRAM has a 16F2 structure, while 4DS makes use of a 4F2 technology.

The real question is whether or not the technology will move into real production. So far, RRAM and other next-generation memory types have failed to live up to their promises. ''With the right partner, we will see our RRAM technology move into production within the next 18 to 24 months,'' he added.