The International Technology Roadmap for Semiconductors (ITRS) is now one of the most important references for the semiconductor industry. It addresses the technological challenges the industry may meet over the next 15 years, indicating possible solutions. Today, all semiconductor-equipment and chip manufacturers follow white papers from the ITRS, when they implement their roadmaps. The first edition of ITRS was published in 1998, and it was co-written by experts from Europe, the US, Japan, South Korea and Taiwan. ITRS 2005 is the 8th edition, and the 9th edition will become available by the end of 2006. In the roadmap to date, ITRS projects that the half-pitch of DRAM will shrink by 30% within a three-year timeframe, so that the roadmap becomes a guideline for the continuing revolution in chip design for deep submicron, bringing IC design into line with the basic precepts of Moore's Law and the transition to metal gates in the development of transistors for microprocessing units (MPUs).
Resolution Enhancement Technology; EUV: Extreme UltraViolet;
EPL:Electron Projection Lithography; ML2: Maskless Lithography; PEL:
Proximity Electron Lithograph; LFD -Lithography Friendly Design rules
What comes beyond 193nm immersion lithography...
Ever since Intel co-founder Gordon Moore introduced the so-called Moore's Law in 1965, the concept of doubling the number of transistors on ICs every 18 months or so has become a key benchmark for semiconductor development. Moore's Law is literally worshipped by scholars, R&D and engineers in all sectors of the industry. If Moore's Law continues to hold true, what will happen to the lithography industry?
Chris A. Mack, vice president of KLA-Tencor, notes that optical lithography is encountering stiff challenges when moving to deep submicron production. He indicates that conventional dry lithography is encountering a bottleneck, as the numerical aperture (NA) approaches 0.9. Changing the wavelength incurs higher costs due to a lack of a mature photoresist. Enhancing resolution via the adoption of OAI (off-axis illumination), no matter whether through the adoption of quadrupole or cross-quadrupole light sources, involves linear issues.
There are many new technologies in development, including 157nm, 193nm immersion and extreme ultraviolet (EUV) lithography. Which of these will eventually prevail? The ITRS 2005 update seems to have come to a conclusion. It thinks the 193nm scanner (including the use of wet scanners) will be the mainstream solution at the next two technology nodes. If one day water-based immersion technology can be extended in its application, the use of fluid rather than air for lithography will be the star technology for the 32nm and 22nm environments.
Although pure water can deliver a refractive index of 1.44, moving beyond 45nm demands a higher NA value and accelerates the demand for a medium with a higher refractive rate than that of pure water. JSR and Mitsui Chemicals (MCI) have both presented solutions for meeting the challenges of production at 32nm. JSR has developed a refractive index solution that combines high transparency with low viscosity, to allow a refractive index of 1.64. MCI has also introduced "Delphi," which claims to project lines and spaces (L/S) at a resolution that enables lithography for 32nm.
High purified solution could edge the resolution of lithography down to 32nm design rule...
The existing photolithography tool market is occupied mainly by ASML, Canon, Nikon and the smaller-scale Ultratech Steppers. ASML bought the world's fourth largest toolmaker, Silicon Valley Group (SVG), in May 2001, and the move pushed ASML to the top spot in the lithography tool rankings. The toolmaker has gained considerable market share, globally, over the past two years. In 2005, its share of the lithography market rose as high as 55%.
At Semicon West 2005, ASML Taiwan showcased the TWINSCANTM XT:1700Fi, which is scalable to 45nm. This is ASML's fourth-generation 193nm immersion scanner (the previous three were the XT 1150i, XT 1250i and XT 1400i). As of the first quarter of 2006, ASML had sold 14 immersion scanners worldwide at a per unit price of about US$30 million. In response, Nikon, the runner up, introduced the NSR S609B and Canon, with a global number-three ranking, rolled out the FPA-6000 AS4i.
According to Gartner Dataquest, in 2006 the worldwide lithography market will grow 17% on-year to reach US$5.85 billion. Gartner expects growth to continue until 2009, when it will have become a US$7 billion market. This year, between 15 to 20 193nm immersion scanners will be sold. An increasing number of immersion steppers will be sold in the future, as chipmakers move to more advanced technologies. By 2010, 120 immersion steppers will be sold annually.
CMP demand picks up along with copper process
As silicon devices become smaller and smaller, and interconnect layers become larger and larger, resistance increases, and an RC time delay can be induced by oxidation in the metal line, for the duration of its lifetime. This delay may limit the entire performance of the device and become a critical aspect of the technology. One of the increasingly popular solutions is to replace traditional aluminum interconnects with copper. The use of a copper process can reduce the number of interconnect layers, simplify what is normally a complex process and cut manufacturing costs by 20-30%.
Nevertheless, while most dry etch processes can be implemented in aluminum alloy, copper is more difficult to etch. Instead, process engineering utilizes a Copper Damascene metallization process to replace the earlier Subtractive Etch process. Chemical vapor deposition (CVD) and physical vapor deposition (PVD) have been the two most common approaches to metal deposition in the past. However, these two approaches are not ideal for copper deposition because the copper lines are embedded in the arrays, in contrast to electroplating. Following electroplating, the surface of the wafer will have scratches, copper holes or other irregularities on the surface of the wafer. The chemical mechanical planarization (CMP) process is then necessary, to remove these anomalies.
The result is that chemical mechanical planarization (CMP) has taken on an increasingly role with the advance to 12-inch wafer fabrication and, simultaneously, a migration to the 65nm process node. Since the migration to deep submicron process demands high accuracy for lithography, the growing complexity of lithography requires a higher level of planarity of the interlayer dielectric (ILD) and metal surface.
The market for CMP equipment will grow by 10% to US$1.13 billion in 2006, according to Gartner. Although the market should stay flat in 2007, it will enjoy explosive growth from 2008, as DRAM makers migrate to 65nm production. Accordingly, the research firm estimates that the market for CMP tools will hit US$1.8 billion in 2008.
During the CMP process, chemical slurry or reagent will be pumped in for planarization, either by etching or grinding, to even out any irregular topography. However, the CMP process itself can introduce undesirable effects, and these may eventually impact yields and interconnect performance. These potential side-effects underline the importance of the choice of materials and the need to avoid oxide erosion.
Source: Crystec Technology Trading
Source: Applied Materials.
Source: IEEE Transactions on Semiconductor Manufacturing, Vol. 18, May 2005.
used to be the leading tool supplier in the early stages of development
of CMP, but later it continued to lose market share to competitors such
as Applied Materials and Ebara. From 1999, Applied Materials began to
dominate the market, taking a 70% market share. In 2004, Applied
Materials introduced the Reflexion LK electro-chemical mechanical
planarization (ECMP) tool. This CMP tool is able to remove bulk copper
electrically, reducing the cost of consumables significantly and
replacing expensive slurries for copper with low-cost electrolyte