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Intel 22nm 3D Tri-Gate FinFETs Transistors: Faster, Cooler, Smaller

"The 22nm 3-D Tri-Gate transistors provide up to 37% performance increase at low voltage versus Intel's 32nm planar transistors. This incredible gain means that they are ideal for use in small handheld devices, which operate using less energy to "switch" back and forth. Alternatively, the new transistors consume less than half the power when at the same performance as 2D planar transistors on 32nm chips." Jean-Louis Gassée /guardian.co.uk, Monday 9 May 2011 07.07 BST


1.Intel Announces first 22nm 3D Tri-Gate Transistors, Shipping in 2H 2011 / Anandtech

2.The Origins of Intel's New Transistor, and Its Future / IEEE Spectrum


1. Intel Announces first 22nm 3D Tri-Gate Transistors, Shipping in 2H 2011

by Anand Lal Shimpi on 5/4/2011 2:05:00 PM
Posted in  CPUs , 22nm , Intel

Earlier this week Intel sent us a cryptic message:

I wanted to invite you to an Intel press conference on Wednesday May 4th at 9:30am Pacific time. Intel will be making its most significant technology announcement of the year. No further details will be provided in advance. The event will be held in San Francisco so for those of you are local in the SF Bay Area please attend in person if you like. It will also webcasted live. Tune-in details and logistics are below. Please let me know if you can attend.

A while ago Intel decided that a nice way to drive up its stock price would be to behave more like Apple, keeping major announcements under wraps and introducing them on its own terms to hopefully build up anticipation and excitement for Intel's announcements. You've seen examples of this with how closely Intel held Sandy Bridge's architectural details before its presentation at IDF, and how little we knew about Quick Sync (Sandy Bridge's hardware video transcoder) until Intel decided it was time to talk about it.

Apple can get away with it since most of its products are tangible, consumer facing devices. Intel's technologies are arguably even more important, but they're just not as easy for the general populace to get excited about. Today's announcement is the perfect example of just that.

Earlier today Intel announced that its 22nm process would not use conventional planar transistors but rather be the first time Intel is using 3D Tri-Gate transistors. This is a huge announcement that fuels Intel's leadership in the mobile/desktop/server CPU space and makes it a lot more attractive in the SoC space, let's understand why.

The Transistor

Here's a simple diagram of a standard 32nm planar transistor, exactly what you'd find in a Sandy Bridge CPU:

mage Courtesy Intel Corporation

I spent a couple of semesters as a computer engineering student a few years ago studying how these things work. There's a lot of math and it's not fun to do over and over again so we'll ignore all of that for now. The basics are thankfully much more fun to understand.




Image Courtesy Intel Corporation

The goal of a transistor is to act as a very high speed electrical switch. When on, current flows from the transistor's source to the drain. When off, current stops. The inversion layer (blue line above) is where the current flow actually happens.

Ideally a transistor needs to do three things:

1) Allow as much current to flow when it's on (active current)
2) Allow as little current to flow when it's off (leakage current)
3) Switch between on and off states as quickly as possible (performance)

The first item impacts how much power your CPU uses when it's actively doing work, the second impacts how much power it draws when idle and the third influences clock speed.

In conventional planar transistors it turns out that voltage in the silicon substrate impacts leakage current in a negative way. Fully depleted SOI (silicon on insulator) is an option to combating this effect.

The smaller you make the transistors, the more difficult it is to make advancements in all three of these areas all while increasing transistor density. After all not only do you have to worry about keeping power under control, but the whole point to shrinking transistor dimensions is to cram more of them into the same physical die area, thus paving the way for better performance (more cores, larger caches, higher performance structures, more integration).

The 3D Tri-Gate Transistor

A 3D Tri-Gate transistor looks a lot like the planar transistor but with one fundamental change. Instead of having a planar inversion layer (where electrical current actually flows), Intel's 3D Tri-Gate transistor creates a three-sided silicon fin that the gate wraps around, creating an inversion layer with a much larger surface area.


mage Courtesy Intel Corporation

There are five outcomes of this move:

1) The gate now exerts far more control over the flow of current through the transistor.
2) Silicon substrate voltage no longer impacts current when the transistor is off.
3) Thanks to larger inversion layer area, more current can flow when the transistor is on.
4) Transistor density isn't negatively impacted.
5) You can vary the number of fins to increase drive strength and performance.

The first two points in the list result in lower leakage current. When Intel's 22nm 3D Tri-Gate transistors are off, they'll burn less power than a hypothetical planar 22nm process.



Image Courtesy Intel Corporation

The third point is particularly exciting because it allows for better transistor performance as well as lower overall power. The benefits are staggering:

Image Courtesy Intel Corporation

At the same switching speed, Intel's 22nm 3D Tri-Gate transistors can run at 75 - 80% of the operating voltage of Intel's 32nm transistors. This results in lower active power at the same frequency, or the same active power at a higher performance level. Intel claims that the reduction in active power can be more than 50% compared to its 32nm process.

Image Courtesy Intel Corporation

At lower voltages Intel is claiming a 37% increase in performance vs. its 32nm process and an 18% increase in performance at 1V. High end desktop and mobile parts fall into the latter category. Ivy Bridge is likely to see gains on the order of 18% vs. Sandy Bridge, however Intel may put those gains to use by reducing overall power consumption of the chip as well as pushing for higher frequencies. The other end of that curve is really for the ultra mobile chips, this should mean big news for the 22nm Atom which I'm guessing we'll see around 2013.

Image Courtesy Intel Corporation

You'll note that the move to 3D Tri-Gate transistors doesn't negatively impact transistor density. In fact Intel is claiming a 2x density improvement from 32nm to 22nm (you can fit roughly twice as many transistors in the same die area at 22nm as you could on Intel's 32nm process).


Image Courtesy Intel Corporation

It's also possible to vary the number of fins to impact drive strength and performance, allowing Intel to more finely tune/target its 22nm process to various products.

The impact on manufacturing cost is also minimal. Compared to a hypothetical Intel 22nm planar process, the 3D Tri-Gate process should only cost another 2 - 3%

Image Courtesy Intel Corporation

All 22nm products from Intel will use its 3D Tri-Gate transistors.

What Does This Mean

Intel's Ivy Bridge is currently scheduled for a debut in the first half of 2012. Intel is purposefully being vague about the release quarter as Sandy Bridge is doing well and isn't facing much competition at the high end at least.

The impact of Intel's 22nm 3D Tri-Gate transistors on high end x86 CPUs will be significant. Intel isn't expecting its competitors to move to a similar technology until 14nm. The increases in switching speed at the same voltage could allow Intel to finally hit or exceed that magical 4GHz barrier in a stock CPU. I suspect Intel will likely use the gains to deliver lower power CPUs however there's always the possibility of some very fast Extreme Edition parts.

Image Courtesy Intel Corporation.

The bigger story here actually has to do with Atom. The biggest gains Intel is showing are at very low voltages, exactly what will benefit ultra mobile SoCs. Atom has had a tough time getting into smartphones and while we may see limited success at 32nm, the real future is what happens at 22nm. Atom is due for a new microprocessor architecture in 2012, if Intel goes the risky route and combines it with its 22nm process it could have a knockout on its hands.



2. The Origins of Intel's New Transistor, and Its Future

A Q&A with Chenming Hu, coinventor of both the FinFET and its likely competitor

By Rachel Courtland  /  May 2011

9 May 2011—Last Wednesday, Intel announced a big change to the electronic switches at the heart of its CPUs. Going forward, the firm will be using three-dimensional transistors to take the place of long-used planar devices.

The new transistors—dubbed "tri-gates"—are a variation on the FinFET, a transistor design that substitutes the flat channel through which electrons flow with a 3-D ridge, or fin. Popping the channel out of plane and draping the gate—which switches the transistor on and off—over it will allow Intel to shrink the smallest features in its transistors from 32 nanometers to 22 nm while cutting power consumption in half. This feat would be impossible to do with the transistor design the company had been using.

How did this 3-D design win its way into production? We asked the coinventor of the FinFET, IEEE Fellow Chenming Hu, a professor emeritus at the University of California, Berkeley, how the new transistors got their start, why we need them now, and where they will go from here.

IEEE Spectrum: We’ve been shrinking two-dimensional, or planar, transistors just fine for 50 years. Why are we seeing a switch to three-dimensional FinFETs?

Chenming Hu: I’ll distill the problem with planar transistors to a single point. It all stems from the fact that it is very difficult to turn off a transistor when it’s very small. In other words, you can’t stop the current flowing through the transistor when you don’t want the current to flow.

I’ll use an analogy to explain this. There is a garden hose lying on a soggy lawn, and you want to stop the water from flowing into this lawn. If there’s a long hose, you can call your friends to come in and put 10 pairs of hands down, and you can stop the water. Now imagine you shorten the hose so you cannot even put one palm on it to stop it. Now you shorten it even more, so you can only put one finger on it. It’s impossible to stop.

In the past 10 years, people have dealt with this garden hose problem in various ways, and one way has been to sacrifice power. For 250-nm transistors, the power-supply voltage was 2.5 volts; for 180 nm, it was 1.8 V; for 130 nm, it was 1.3 V. The pattern was very regular until 90 nm, but it reached a limit. Instead of 0.9 V, you know what the industry used? 1.2 V. Even at 45 nm, the industry still used 0.9 V instead of 0.45 V.

IEEE Spectrum: So current is leaking even when the transistors are off. To get around that problem, you have to use a higher voltage to make the difference between on and off more obvious?

Chenming Hu: Exactly. What’s the consequence of that? Power is proportional to the square of the voltage. So if you use twice as high a voltage as the historical trend, your cellphone will consume four times the power. The pain is just too big to keep going that way. We thought planar technology would run out of steam sometime after 25 nm, and it did.

IEEE Spectrum: How do FinFETs help fix the leaky garden hose problem?

Chenming Hu: Remember, the hose is on a soggy, soft lawn. So what if instead of pressing your finger on this garden hose, you pinch your fingers on the two sides of the garden hose? That’s the analogy. The weak point, the soggy lawn, is the silicon substrate. So you really have to do something on both sides so you’re pinching against something firm, and that’s what the FinFET is doing. We should pinch the channel [where electrons flow] on two sides and on top. The more pinching sides, the better.

Pinching the hose will allow us to use a much, much shorter hose. That’s extremely important. Making things small is really the key of making the electronics cheaper, faster, and lower power.

IEEE Spectrum: The idea for FinFETs has been around for a while. How did it all get started?

Chenming Hu: DARPA [the Defense Advanced Research Projects Agency] sent out a request for proposals in 1996 for ideas to develop electronic switches beyond 25 nm. At the time, the industry was using 250-nm transistors, and the general view was that transistors could not be scaled below 100 nm. But my students and I had already been thinking about how to get transistors to scale to 25 nm and beyond.

There was a quick meeting probably lasting only five minutes between myself and two colleagues—Professor Tsu-Jae King Liu and Professor Jeff Bokor. The meeting was short because we already knew what to do.

I was on a flight to a conference in Japan, and I had about 10 hours, so I just wrote down the technical proposal in longhand. I proposed two structures that we’d been thinking about for a while. One was FinFETs, and the other is what we call an ultrathin-body silicon-on-insulator (UTB SOI).

We got the contract in 1997, and that gave us the resources to demonstrate FinFETs experimentally. A young graduate student named Xuejue "Cathy" Huang made the working device, and the team of three professors and 11 students and visiting researchers published it in 1999.

IEEE Spectrum: How did the industry react to the FinFET paper?

Chenming Hu: It was an instant hit. I remember Cathy and I were invited to Intel Santa Clara just a couple of months after the publication, and in that same year, 2000, I was invited to Intel Oregon twice. At the time, people were asking me how long it would take for the idea to get into production. I said about 10 years, so I guess I was off by one.

IEEE Spectrum: Was the attention that you got unusual for a new transistor design?

Chenming Hu: Extremely unusual. We contributed two things: We figured out a way to make the transistor manufacturable, and we showed how this thing could bring us to 25 nm and to 10 nm. We even figured out how to use the FinFET to solve the two top problems plaguing MOSFETs today—random variations of impurity atoms and variations in gate length (roughly the distance from the source to the drain). So we anticipated a lot of emerging problems and showed that FinFETs can solve them. That was really the first time that the industry believed there was life [after 25 nm].

IEEE Spectrum: What have been the challenges in getting FinFETs to market?

Chenming Hu: In production, there are two areas: One is getting the manufacturing variation controlled well. When you add a fin, then you have to make sure the fin’s height and width are uniform. Probably a bigger limitation is the interaction between the transistor and the circuit design. Intel has the benefit of being a vertically integrated company where the designers and technologists work under the same roof.

IEEE Spectrum: What about the other design you proposed to DARPA, the UTB SOI? How does that design work, and how has it been progressing?

Chenming Hu: SOI has a layer of insulator with a thin layer of silicon on top. Instead of a thick regular round hose, UTB is like a thin, flat hose—one of those compact garden hoses that’s easy to roll because it’s almost like tape. You can pinch with one finger from the top, because the hose is very thin, so you don’t have to push down much.

IBM has been making SOI processors for years, and even today it uses about 40-nm-thick silicon. To get to 20-nm transistor size, you have to use very thin, say, 5-nm silicon. When we proposed this, nobody in the world could provide SOI substrates with such thin and uniform silicon film. Five nanometers is very thin; it’s only about 15 silicon atoms or so in thickness. But the amazing thing is, two years ago, an SOI substrate company called Soitec announced that they can make such a thin film, and they have given samples to many companies, including IBM.

IEEE Spectrum: FinFET transistors are the first to market, but could UTB SOI transistors ultimately win out?

Chenming Hu: Starting in 2002, both FinFET and UTB SOI were listed in the International Technology Roadmap for Semiconductors (ITRS). That’s an industry consensus of what’s needed to keep the industry going. They are the only two that are listed as the likely successors of the planar MOSFET.

I think there’s room for both, at least in the short term. UTBs need less manufacturing and design development work than FinFETs, because UTBs rely on something that the semiconductor manufacturers do not have to make. But the UTB wafers cost extra money—several hundred dollars more—so it’s going to add to the cost. There may be savings in device fabrication cost, which is difficult to estimate.

I think some companies, clearly Intel and some larger companies, will go with FinFETs, and some smaller companies will go with UTBs. Once both are in production, then people will be able to compare the benefits side by side very easily—the economics as well as the performance.

IEEE Spectrum: Does one offer a clear advantage over the other?

Chenming Hu: Staying with the hose analogy, when you have a big thick hose, you can carry more current, so it’s good for high speed. So that’s why I think the large companies that can make the investment in FinFETs will probably do it, because FinFETs are versatile. For the companies that need to have a quick way to get beyond 22 nm, I think UTB is a viable technology, especially for those companies that already have experience with the SOI. The shortcoming, of course, is the flat hose—with such thin silicon, less current goes through, which translates to lower speed.

IEEE Spectrum: Some industry leaders have been quoted as saying FinFETs won’t be as good for low-power applications as UTBs.

Chenming Hu: I think FinFETs are good for low power as well, but it does take more investment to bring them to production. I think a healthy competition will ensue. The fact is, the two technologies could coexist for a while, which is a good thing for the industry and certainly a very good thing for consumers.