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News articles - Intel, IBM, NEC announce Hi-k, Metal gate Breakthrough

           1. Intel and IBM give Moore's Law a boost

           2. Intel tips high-k, metal gates for 45-nm

           3.  Intel tips 45-nm process, demos chips

           4. IBM and partners tip high-k, metal gates

           5. NEC offers platform for cell-based ICs

           6. NEC says 55-nm process cuts power consumption

 

Intel and IBM give Moore's Law a boost
 

Michael McManus, DigiTimes.com, Taipei [Sunday 28 January 2007]

Intel and IBM have separately made claims of breakthroughs in transistor design that should lead to improved design in sub-micron process technology by reducing the amount of electrical leakage, and extend Moore’s Law into the next decade

According to Moore’s Law, the number of transistors on a chip roughly doubles every two years and to maintain this pace of innovation, transistors have had to continue to shrink to ever-smaller sizes. However, using current materials, the ability to shrink transistors is reaching fundamental limits because of increased power and heat issues that develop as feature sizes reach atomic levels.

Intel stated that it is will use two new materials to build the insulating walls and switching gates of its 45nm transistors. For its 45nm production, Intel will use a new material with a property called high-k for the transistor gate dielectric, and a new combination of metal materials for the transistor gate electrode. Intel Co-Founder Gordon Moore noted that the implementation of high-k and metal materials marks the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s.

Silicon dioxide has been used to make the transistor gate dielectric for more than 40 years because of its manufacturability and ability to deliver continued transistor performance improvements as it has been made ever thinner. For example, Intel has been able to shrink the silicon dioxide gate dielectric to as little as 1.2nm thick – equal to five atomic layers – on its 65nm process technology.

But the continued shrinking has led to increased current leakage through the gate dielectric, resulting in wasted electric current and unnecessary heat. Transistor gate leakage associated with the ever-thinning silicon dioxide gate dielectric is recognized by the industry as one of the most formidable technical challenges facing Moore’s Law, Intel pointed out.

To solve this critical issue, Intel replaced the silicon dioxide with a thicker hafnium-based high-k material in the gate dielectric, reducing leakage by more than 10 times compared to the silicon dioxide used for more than four decades.

Because the high-k gate dielectric is not compatible with today’s silicon gate electrode, the second part of Intel’s 45nm transistor material recipe is the development of new metal gate materials. Intel declined to name the specific metals it will use, but the company will use a combination of different metal materials for the transistor gate electrodes.

Intel claims that the combination of the high-k gate dielectric with the metal gate for its 45nm process technology provides more than a 20% increase in drive current, or higher transistor performance. Conversely it reduces source-drain leakage by more than five times, thus improving the energy efficiency of the transistor, the company stated.

Intel believes it has extended its lead of more than a year over the rest of the semiconductor industry with the first working 45nm processors of its next-generation 45nm family of products – codenamed Penryn. The company said it has five early-version products up and running – the first of fifteen 45nm processor products planned and it remains on track for 45nm production in the second half of this year.

However, IBM also announced that it has made a breakthrough in high-k metal gate development. Working with AMD, Sony and Toshiba, IBM said it has already inserted the technology into its semiconductor manufacturing line in East Fishkill, NY and it will also apply the technology into 45nm production starting in 2008.

 

Intel tips high-k, metal gates for 45-nm

Mark LaPedus
  SAN JOSE, Calif. — Intel Corp. has disclosed more details about its 45-nm process, saying that it has implemented high-k dielectrics and metal gates for the technology.

The company claims to be one of the first chip makers to implement these new materials in its process technology. Using an undisclosed thick hafnium-based material for its high-k films in gate-stack applications, Intel claims that it is able to boost the overall performance, while also reducing transistor leakage by more than 10 times over current silicon dioxide technology.

Seeking to get a jump on its rivals, Intel (Santa Clara, Calif.) (see below- Intel tips 45-nm process, demos chips) disclosed the initial details of its 45-nm process and claimed it had produced the world's first chips based on the technology. Intel's 45-nm process, dubbed P1266, is said to incorporate copper interconnects, low-k dielectrics, strained silicon and other features.

At the time, the company did not disclose if it would deploy silicon dioxide or high-k dielectric films for the critical gate stack. Now, Intel said it will use a new material with a property called high-k, for the transistor gate dielectric, and a new combination of metal materials for the transistor gate electrode.

''The implementation of high-k and metal materials marks the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s,'' said Intel co-founder Gordon Moore, in a statement.

''As more and more transistors are packed onto a single piece of silicon, the industry continues to research current leakage reduction solutions,'' said Mark Bohr, Intel senior fellow, in the same statement. ''Our implementation of novel high-k and metal gate transistors for our 45-nm process technology will help Intel deliver even faster, more energy efficient multi-core products that build upon our successful Intel Core 2 and Xeon family of processors, and extend Moore's Law well into the next decade.''

NEC Corp. is moving high-k into production, while IBM Corp. has disclosed the technology as well.

Intel tips 45-nm process, demos chips

Mark LaPedus
  SAN JOSE, Calif. — Seeking to get a jump on its rivals, Intel Corp. on Wednesday (Jan. 25) disclosed the initial details of its 45-nm process and claimed that it has produced the world’s first chips based on the technology.
 

Compared to its 65-nm process, Intel (Santa Clara, Calif.) claims that its new 45-nm technology has a two-fold improvement in transistor density, a 20-percent jump in switching speeds and a 30-percent reduction in power. Since late last year, Intel has been shipping microprocessors based on its 65-nm process.

Intel’s 45-nm process, dubbed P1266, is said to incorporate copper interconnects, low-k dielectrics, strained silicon and other features. The company did not disclose if it would deploy silicon dioxide or high-k dielectric films for the critical gate stack.

It plans to manufacture 45-nm devices by using 193-nm “dry” lithography scanners — instead of immersion tools, as previously expected by some analysts.

With the 45-nm process, the microprocessor giant also said it has manufactured a prototype, 153-Mbit SRAM based on the technology. Measuring 119-mm2 Intel’s “shuttle test” device is a six-transistor chip that boasts a cell size of only 0.346-micron2 according to the company.

The 45-nm device includes several components on the same chip, including an SRAM array, PROM array, phase-lock-loop, I/O, register file and a discrete test structure, according to Intel.

The announcement demonstrates that Intel’s 45-nm process is on track and expected to be ready for mass production in the second half of 2007, said Mark Bohr, an Intel senior fellow and director of process architecture and integration.

Despite recent 45-nm announcements made by NEC, Toshiba and other chip makers, Intel claims to be the leader in this technology arena. “I think it’s safe to say that we’re ahead,” Bohr said. “I’ve seen the other announcements, but they don’t have the level of detail that we’re talking about.”
 

Bohr declined to comment on the specifics of Intel’s 45-nm process, but he disclosed that the company is still not considering the use of silicon-on-insulator (SOI) technology. For years, Intel has dismissed the need to use SOI. “This technology will continue to use strained silicon,” he said. “We’re not using SOI.”
 

In contrast, microprocessor rival Advanced Micro Devices Inc. recently signed a technology license for "floating-body" silicon-on-insulator (SOI) memory developed by startup company Innovative Silicon Inc. AMD (Sunnyvale, Calif.) said it is interested in the Z-RAM (zero capacitor) technology for use in its microprocessors.
 

The embedded memory is a good fit with AMD, which has moved all its microprocessor production over to SOI manufacturing processes.
 

Intel and AMD are preparing to square off again in the x86-based processor market with next-generation products, which are due out in 2006.
 

Intel recently outlined its strategy to fend off competitive pressures from AMD, especially at the 65-nm node. At an event, Intel reannounced its roadmap of dual-core mobile, desktop and server processors at the 65-nm node. The company also claimed that it will have no less than four wafer fabs in its arsenal that will manufacturer chips based on the 65-nm process.
 

Intel has also announced three 300-mm fabs capable of 45-nm chip production, including the D1D plant in Oregon, Fab 32 in Arizona and Fab 28 in Israel. In 2005, Intel has invested more than $4 billion in new fabs and upgrades.


NEC offers platform for cell-based ICs

Yoshiko Hara
  TOKYO — NEC Electronics Corp. has started offering its CB-55L platform for cell-based ICs developed on its UX7LS 55-nm process technology.

NEC introduced high-k film in the volume production process. "We are preceding competitors by a half step," claimed Hiroshi Iguchi, vice president of NEC's 1st Systems Operations Unit.

NEC wants to expand sales of cell-based ICs from the current 75 billion (about $625 million) to 120 billion ($1 billion) by 2010 based on sales related to the CB-55L platform.

CB-55L is based on NEC Electronics' UX7LS CMOS process technology, which the company claims is the first 55-nm process to utilize a high-k dielectric. The introduction of the high-k dielectric would reduce leakage current to one-fourth and would improve total power consumption by 40 percent over the previous 90-nm generation introduced in 2002.

Power consumption for the CB-55 is 1.7 nano-watt/MHz/gate. The use of (see below - NEC says 55-nm process cuts power consumption) makes it possible to increase gate density by 230 percent, enabling 925,000 gates per square millimeter. The maximum number of gates that can be integrated on a chip is 100 million, and the maximum number of I/Os is 2,800. Power supply voltage is 1-1.2V internally and I/O at 1,8V, 2.5V and 3.3V. The maximum system frequency is 450 MHz with 1.2V power supply and 233 MHz with 1.0V supply.

NEC will drop the high-speed version and intends to cover middle and low power types with the CB-55L. "At present, we have no intention to develop the high-speed type. It accounts for just less than 10 percent of the total CB-90 sales. We want to concentrate on the low-power type aiming at portable devices," Iguchi said.

NEC will provide IP macros such as USB2.0, JPEG, DDR/DDR2 focusing on targeted applications such as digital cameras, camcorders and other battery-operated applications. It will also offer commodity IPs, including PLLs, A/D converters and D/A converters. The library will be available in March.

When NEC Electronics announced its UX7LS in November 2005, the company said immersion lithography technology would be used for critical processes. But Iguchi said CB-55L can still use dry process technology.

 

NEC says 55-nm process cuts power consumption

Yoshiko Hara
  TOKYO — NEC Electronics Corp. announced Monday (Dec. 5) that it has developed a 55-nm node process named UX7LS that will employ immersion lithography and higher dielectric constant (high-k) material. The company claims the process provides one-tenth lower power consumption in both operating and stand-by modes than 65 nm processes.

"UX7LS is an improved version of the 65-nm process. By combining with the 65-nm process technology with high-k film, we've developed the ultimate low power LSI," said Takaaki Kuwata, general manager of Advanced Device Development Division of the company. "The process will be applicable to LSIs for products from mobile phones, mobile consumer products to network systems," he said.

NEC Electronics had disclosed a 65-nm process named UX7, which employs conventional dry lithography and a transistor structure without high-k technology. Engineering samples of both high speed and low power versions will be available by the middle of next year.

"Just by scaling down to 55-nm, the power consumption can not be lowered," said Kuwata. "Our Ultimate Low Power technology, including the Vdd (source voltage)/Vth (threshold voltage) control and high-k technology realized low power consumption."

The NEC Electronics team used the combination of body-bias sensitive device structure to control transistor threshold voltage and high-k (HfSiON) gate insulating film to realize the low power devices. The high-k gate insulator film is grown on the conventional SiO2 layer at the gate. The high-k insulator layer is equal to 1.8nm thick SiO2 layer.

"We can supply the highest density and smallest SRAM around 2007 to 2008, which will be the most advanced device until the 45-nm node products become available on the market," said Kuwata. The SRAM on the UX7LS process will have a gate density of 925,000 gates per square millimeter and cell size of 0.432 square microns.

The company intends to offer samples in summer 2007 and begin volume production within the year.

It is an advantage that most 65-nm production facilities can be used for the 55-nm process, said Kuwata. Only for critical processes will they use the emersion lithography system. ASML will supply the emersion lithography system for sample fabrication and pilot production. The volume production system has not yet been decided, according to Kuwata. The first metal layer will have a 180-nm pitch.

NEC Electronics announced the joint development agreement with Toshiba for the 45-nm node and beyond technologies. The UX7LS technology will eventually be merged into the jointly developed process, tentatively designated UX8.

Based on the joint 45-nm process, NEC Electronics will continue developing differentiated technologies such as embedded DRAM independent from its partner, according to Kuwata.