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Interconnect Issues and 45 nm Process


1.Interconnect Issues Going Into 45 nm/ Semiconductor International

2. ULSI Semiconductor Atlas - 'Interconnect' /ULSI Semiconductor Atlas

3. Microchip Fabrication - 'Interconnect' /Microchip Fabrication

4. Fundamentals of Semiconductor Manufacturing - 'Interconnect' / Fundamentals Semiconductor Manufacturing



1. Interconnect Issues Going Into 45 nm


Laura Peters, Senior Editor -- Semiconductor International, 6/15/2006

Several trends are making interconnect processing more challenging as the industry moves to more advanced technology nodes. One is the issue of resistance variability, which is a function of things such as across-wafer variability of CMP, etch and other processes, making process control paramount. Parametric variation is an verall challenge below 100 nm, not just for interconnects.

Another issue is the size effect — the increased resistivity of copper as linewidths shrink below around 100 nm and approach the mean free path of electrons in copper (39 nm). The resistivity increase is caused by electron scattering at the surface of the line and at grain boundaries. Fortunately, the estimations of the magnitude of the effect the size effect has on interconnect delay has been overestimated. For at least the next few device generations, the size effect can be effectively managed through interconnect design, including keeping local interconnects short. In addition, a change of barrier material would have little effect on the intrinsic surface scattering of copper (Figure ).1

Finally, current density is increasing because the size of the lines is shrinking, yet the current flowing through the copper is the same. The thinner lines must be better protected from electromigration. Cobalt capping layers would help in this regard, but there are other levels of redundancy that chipmakers are employing.

A thin-film scattering of large grain copper for a variety of barrier films. Resistivity vs. thickness is consistent with 100% diffuse scattering in all cases. (Source: Novellus)

In advanced logic devices, where most companies have successfully made the transition to copper interconnects and the first generation of low-k dielectrics (k~2.9), the resources are now being invested in second-generation low-k (~2.5) for the 45 nm node. Beyond curing, other film treatments are being developed to give films the necessary electrical properties without having to occupy the same footprint. For second-generation low-k, the challenge largely lies in developing damage- and moisture-resistant films that can undergo dual-damascene processing and packaging via flip-chip and wire bonding.2

Reliability in copper interconnects is tied to the weakest interfaces, inducing stress migration and electromigration phenomena. The other major mode of electrical failure is time-dependent dielectric breakdown associated with weaker dielectrics. Therefore, building reliable interconnects comes down to engineering interfaces and managing stresses in the on-chip stack, as well as stresses through the off-chip assembly and packaging process.

Memory manufacturers are expected to start adopting copper next year. Unlike the logic manufacturers, some memory makers adopted some form of low-k dielectric prior to making a metallization change from aluminum to copper. Aluminum metallization processes have been extended many ways, including with advanced CVD processes.

From a unit process standpoint, the greatest need seems to be for an ALD barrier solution that would allow more drastic scaling of the barrier, which leads to an equivalent lower keff without changing the dielectric. But the magical Ta/TaN PVD barrier will continue to be extended for now. Likewise, while CoWP capping processes are being made more manufacturable, better dielectric caps will continue to be developed. It is unclear whether CoWP capping layers will ever be implemented in manufacturing or if an alternative copper metallization scheme will come along.

TechXPOT: Challenges in Device Scaling

Wednesday, July 12: Interconnect Technology for 45 and 32 nm
Copper interconnect technology is evolving rapidly with ultrathin barrier layers, better controlled metal deposition, advanced planarization processes, and new dielectric materials, but is it enough? Will the industry be forced to go to 3-D architecture to meet performance requirements?
Session Chair: Ken Monnig
11-11:20 a.m. AMD, Cathy Labelle — Opportunities for New Materials
11:20-11:40 a.m. SEZ, Ernst Gaulhofer — Surface Preparation Challenges for 45 and 32 nm
11:40 a.m.-12 p.m. Metara, Tom Bailey — Copper Process Control
12-12:20 p.m. Cabot, Paul Feeny — Planarization Challenges for Sub 65 nm Technologies
12:20-12:40 p.m. Tezzaron, Bob Patti — 3D Architecture

  1. G.B. Alers, "Containing the Finite Size Effect in Copper Lines ," Semiconductor International , May 2006.
  2. L. Peters, "Making Low-k Dielectrics Work ," Semiconductor International , June 2006.





2.ULSI Semiconductor Atlas - 'Interconnect'

By Chih-Hang Tung, George T. T. Sheng, Chih-Yuan Lu, Contributor George T. T. Sheng, Chih-Yuan Lu
Wiley-IEEE, 2003


Ultra Large Scale Integration (ULSI) refers to semiconductor chips with more than 10 million devices per chip. ULSI Semiconductor Technology Atlas uses examples and TEM (Transmission Electron Microscopy) micrographs to explain and illustrate ULSI process technologies and their associated problems.

The first book available on the subject to be illustrated using TEM images, ULSI Semiconductor Technology Atlas is logically divided into four parts:
* Part I includes basic introductions to the ULSI process, device construction analysis, and TEM sample preparation
* Part II focuses on key ULSI modules--ion implantation and defects, dielectrics and isolation structures, silicides/salicides, and metallization
* Part III examines integrated devices, including complete planar DRAM, stacked cell DRAM, and trench cell DRAM, as well as SRAM as examples for process integration and development
* Part IV emphasizes special applications, including TEM in advanced failure analysis, TEM in advanced packaging development and UBM (Under Bump Metallization) studies, and high-resolution TEM in microelectronics


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Page 5
The list is growing as new interconnect challenges emerge. Over the years the Kilby principles have demonstrated their validity with dramatic improvements ...
Page 14
... from out-of-focus layers in a sample have yielded better results in imaging microelectronics circuits with multiple layers of interconnect structures. ...
Page 55
For the design rules used in the l to 5 um technology nodes, the interconnect delays were typically much smaller than device switching times {eg, 50 MHz), ...
Page 56
... interconnects were introduced in about I998 to replace Al. However, W and Al layers are still included because of their maturity, as local interconnect ...
Page 57
Therefore the introduction of Cu not only reduced the interconnect electric resistivity but also improved electromigration reliability (to be discussed ...
Page 58
The metallic barrier layer thicknesses must be held on the order of l5% to 25% of the overall metal feature size to retain an acceptable interconnect ...
Page 59
Fewer phonons will be available to transport thermal energy out of the interconnect system. Porous dielectrics have much poorer mechanical and thermal ...
Page 88
What remains to be done on top of this substrate is to isolate and interconnect the structures. It is thus more important to look at the heterostructure ...
Page 154
... the parasitic MOSFET, which is unavoidably formed by active interconnect lines running over the ...
Page 257
The advantages of further scaling down are offset by the interconnect resistance at the gate level. In order to reduce the gate materials' thin film sheet ...
Page 302
... For submicron circuits, laminate-layered interconnect films are often used to alleviate the shallow junctions and high current density problems. ...
Page 318
8.4 MULTILEVEL INTERCONNECT AND VIAs Submicron circuits usually require interconnections at multiple levels to improve area utilization in the reduced chip ...
Page 320
... ii 2 nm Figure 8.44 Multiple-level interconnect VIA chain test structure. Figure 8.45 A VIA chain test structure shows the effect of the ...
Page 328
... not provide the most robust diffusion in terms of material and process but can be integrated easily, and cost effective for Cu interconnect structures. ...
Page 347
... poly layers Forms gates for cell and peripheral devices Forms ILD Forms interconnect the LOCOS oxidation are identical to those of a logic CMOS device. ...
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is on the thin gate oxide and serves as a transfer gate, while the second one is seen on the top of the capacitor and is the poly interconnect runner when ...
Page 362
I9 lM DRAM with polysilicon (PI) as the capacitor plate, polysilicon (P2) as the word line and transistor gate, and Al as the bit line and interconnect ...
Page 363
... AI as the bit line and interconnect, and the bit-line contact (BC), The LDD process with a nitride cap is used in this new technology. ...
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... buried contact (BC) Form poly l local interconnect through BC, Deposit first poly (WSi,), mask etch poly l Form all device gates Mask, implant N-, N+, ...
Page 526
As the device shrank to the critical size where its performance began to depend on the interconnect RC delay, the technology began to diverge toward logic ...





3.Microchip Fabrication: A Practical Guide to Semiconductor Processing-'Interconnect'


By Peter Van Zant
Edition: 5, 2004

semiconductor fabrication process from raw materials through shipping the finished, packaged device. Challenging quizzes and review summaries make this the perfect learning guide for technicians in training. * NEW chapter on nanotechnology * NEW sections on 300mm wafer processing * Processes and devices, and Green processing * Every chapter updated to reflect the latest processing techniques


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4.Fundamentals of Semiconductor Manufacturing and Process Control -'Interconnect'


By Gary S. May, Costas J. Spanos, Contributor Gary S. May


A practical guide to semiconductor manufacturing from process control to yield modeling and experimental design

Fundamentals of Semiconductor Manufacturing and Process Control covers all issues involved in manufacturing microelectronic devices and circuits, including fabrication sequences, process control, experimental design, process modeling, yield modeling, and CIM/CAM systems.

Following an overview of manufacturing and technology, the text explores process monitoring methods, including those that focus on product wafers and those that focus on the equipment used to produce wafers. Next, the text sets forth some fundamentals of statistics and yield modeling, which set the foundation for a detailed discussion of how statistical process control is used to analyze quality and improve yields.,M1

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