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Low-k Dielectrics Status and 45 nm Process


1. Making Low-k Dielectrics Work/ Semiconductor International

2. ULSI Semiconductor Atlas - 'Low-k Dielectric' /ULSI Semiconductor Atlas

3. Microchip Fabrication - 'Low-k Dielectric' /Microchip Fabrication

4. Fundamentals of Semiconductor Manufacturing - 'Low-k Dielectric' / Fundamentals Semiconductor Manufacturing



1. Making Low-k Dielectrics Work

Laura Peters, Senior Editor -- Semiconductor International, 6/1/2006

At a Glance
Engineers have brought low-k dielectrics into manufacturing for 90 nm production. Now the challenge is integrating the next-generation solutions for 45 nm. Will this be pushed to 32? Everything hinges on the reliable integration and packaging of these advanced materials.

In the past couple of years, engineers have accomplished what once seemed impossible: making low-k dielectrics work in commercial ULSI logic devices. The surmounted hurdles have been many: from achieving good adhesion between various dielectric and metal interfaces to finding the right stress relief underfill materials. This accomplishment marks one of the most difficult new materials integration challenges the industry has faced to date.
The implementation of low-k dielectrics in advanced chips is spurred by the need to decrease capacitance and shorten RC delay. However, just as important today is the issue of power consumption (CV2f).

Though it is hard to talk in generalities about low-k implementation (every chipmaker has its own integration scheme, processes and roadmap), having successfully integrated first-generation low-k dielectrics (k~2.9) into leading-edge logic devices for 90 nm, many companies have largely passed down the material and process integration scheme to the 65 nm generation, but with optimized intermediary dielectric layers for lowest effective k value (keff).

Now, there is great debate over what materials will go into the 45 nm devices. "For 45 nm and some high-performance 65 nm, we see leading manufacturers are using 2.5 material, which we believe will carry into the initial phases of the 32 nm node," said Farhad Moghadam, senior vice president and general manager of the Thin Films Product Business Group at Applied Materials (Santa Clara, Calif.). Dan Vitkavage, technology director for low-k films at Novellus (San Jose), agrees "that while many companies are saying that 2.4 or 2.5 is their goal for 45 nm, they say, 'If I can't find integration solutions by a certain date, then I do have a backup approach using a 2.7 film that doesn't have a porogen in it.'"

"Part of the challenge is that people are planning for two generations — 45 nm and 32 nm — and there's definitely a balancing act between major changes at the transistor and back-end-of-line," said Leo Archer, vice president of emerging technologies worldwide at SEZ (Phoenix). Even within other back-end material selections, things are not set in stone. It is unclear whether ALD barriers will be needed for the 32 nm node, and if so, the ALD-like film may need to be used in conjunction with a PVD barrier initially. Selective CoWP barriers may also be needed for 32 nm. All this will influence the adoption of second-generation low-k.

Though CVD solutions involving silicon oxycarbide films (SiOC) with various methyl group configurations make up the vast majority of the solutions used to date, there are alternatives, such as a spin-on material, nanoclustered silica (k=2.25), or air gap approaches, that use more standard dielectrics and strategically formed spaces to get as close as possible to the ultimate dielectric constant of air (k=1). But by and large, CVD solutions provided by Applied Materials, Novellus and ASM International (Bilthoven, Netherlands) are the most widely used in production. The porous versions of these films (k~2.5) are in early pilot line production.

One of the reasons the change at 45 nm will be so substantial is not just the change from a so-called "dense" or solid low-k dielectric to a porous low-k dielectric, but from other major changes at this technology node. Many companies started out with a via-first, trench-last integration scheme. Now, the trench-first hard mask scheme is showing advantages (Fig. 1 ). Moghadam said some companies are switching from via-first to trench-first to get a handle on resist poisoning, and that hard mask schemes are becoming more common to assist in patterning. This change also widens the process window of etchant gases that can be used.

1. The TFHM architecture features no contact between resist and low-k for easier litho rework and a broader choice of materials. The challenge lies in the final multistep etch.  (Source: Crolles2 Alliance)

The titanium or titanium nitride hard mask is then removed during the overpolish step. One disadvantage to using metal hard masks is the cost. "People are moving to the hard mask schemes to make process integration simpler, not cheaper," said Ivan (Skip) Berry, director of technology at Axcelis Technologies (Beverly, Mass.). But such a change can be enormously challenging. "Any time you change the integration scheme, you invite a lot of trouble because you'll have different failure modes and every integration scheme has its own set of defects you have to address," said Daniel Edelstein, IBM fellow and program manager, low-k CVD BEOL at IBM's T.J. Watson Research Center (Yorktown Heights, N.Y.).

Managing interfaces

Much of interconnect stack engineering comes down to interface engineering. The interface between low-k and barrier metal is particularly critical. For best reliability, with the barrier open step, some companies have gone to a sacrificial liner type of approach where some barrier gets sputtered on the sidewalls to allow continuous copper contact from the via to the line below. "The problem is, when you do that sputtering, it's pretty damaging to the low-k, and the lower the k, the more damage you do to the profiles. That points to an area that needs further work," Edelstein said.

Along with this comes a desire to minimize the number of interfaces in the stack. "Any extra layer can bring in problems, and some of those problems are very subtle," Edelstein said. "For example, having a hard mask might help polishing and might help TDDB because you have a stronger top surface to put a cap onto so the line-to-line leakage might be improved. But, on the other hand, it also prevents you from being able to dry out the film below while you're capping it, so you might have an insidious water problem that you don't find out about until you do full-scale reliability testing." Figure 2 shows some of the integration choices that can be made, tradeoffs in terms of electromigration, stress migration, time-dependent dielectric breakdown (TDDB), and the associated impact on capacitance.

2. Extra films that aid in integration come with reliability tradeoffs, such as electromigration, stress migration, reduced time-dependent dielectric breakdown, and capacitance penalties. (Source: D. Edelstein, IBM)

When dielectric caps are used in CMP, often it is the bulk low-k film that then becomes the dielectric cap at the next node. Companies may migrate to a direct polish (for reduced keff) so that CMP process can then be transferred to the cap CMP.

3. A cross-sectional STEM image shows five levels of integrated Black Diamond II (k=2.5). (Source: Applied Materials, courtesy of Crolles2 Alliance)
Advantages to the trench-first hard mask integration scheme include the ability to use SiCN and nitrogen-containing surface treatments because the risk of via poisoning from photoresist is drastically reduced. Users claim significantly improved adhesion over via-first integration schemes using SiC.1 Figure 3 shows five levels of integrated second-generation low-k (2.5), manufactured using a trench-first hard mask integration scheme.

Cost of ownership

Just as important as the technology is the cost of ownership (CoO), especially with 11 or more metal levels at the 65 nm node. "The big issue in BEOL is making the existing low-k/copper process more cost-effective," Berry said. "The second driver is pushing k value lower." Archer agrees that cost issues dominate industry decisions. "As we become more of a commoditized industry, that balance between implementing the technology and maintaining the cost structure has really made the job that much more difficult," he said.

For these reasons, each unit process is also pushed on CoO and process efficiency. "Obviously, on the porous low-k, the cost adder is the cure," Moghadam said. "However, this cost is offset by productivity gains since thinner films are used. For instance, the barrier/seed for the 90 nm was 1000 Å, but it's 200 Å at 65 nm. So overall, the cost of ownership is about the same."

With respect to cleaning processes, Archer said, "The cleans will involve polymer removal, not a major change from what is done today, and driven by the etch. But if companies go to an all-wet strip out of concern for plasma damage, there will initially be a two-chemistry approach, to clean the resist and residue, then clean up the barrier, but eventually they will want one chemistry to do all that. The challenge is maintaining selectivity between low-k dielectrics and ARCs that are not that dissimilar." He emphasized that the clean process is always dictated by the integration scheme, which is specific to each customer. Between metal hard masks, organic and inorganic BARCs, trilayer resist schemes, and etch, each brings complexities in terms of selectivity.

Similar things can be said of CMP processes. The ability to stop on the film of interest and achieve planarity without too much film loss is an ongoing challenge. Typically, a polish is removing copper, barrier, low-k and stopping on a lower k, usually a softer film than the one above it. Since interface quality is so critical, it does not help that porous materials have a smaller surface area for interface strength. "Mechanically weaker dielectrics with thin metal lines are more susceptible to structural damage, where dielectric breaks and discontinuities can occur, even if the lines themselves are not deformed, which they sometimes can be," explained Paul Feeney, senior technologist with Cabot Microelectronics (Aurora, Ill.). The first copper and barrier CMP processes had low selectivity to the barrier, but the film loss became unacceptable with more advanced processes. "Stopping on the dielectric under the barrier is aided by softer pads that minimize defects, but then you can have some non-uniformity issues center-to-edge. A harder pad helps the planarity, but the defect levels need to be contained, which is helped some by lower solids containing slurries," he said. Slurries with lower solids content have been developed specifically to increase the chemical removal component in CMP while reducing the mechanical component. A key challenge throughout CMP is dealing with changing hydrophobicity/hydrophilicity, which can even be intermingled at a single process point. An alternate approach is electrochemical CMP (ECMP), which uses essentially zero downforce and so is compatible with the softer low-k films.

"Much of the burden on the copper CMP step has been transferred to the barrier polish step," said Feeney. For the 2.5 k dielectrics, new slurries are being developed, especially for direct polish on low-k. Achieving good performance in terms of pattern sensitivity, die scale topography and wafer-to-wafer sheet resistance uniformity control is extremely challenging. In a recent study by H.H. Kuo and colleagues at TSMC's Advanced Module Technology Division (Hsinchu, Taiwan), a slurry was designed to meet a self-stop concept, and the impact of an existing etch/ash/linear removal/clean process on the copper CMP process was assessed.3 Self-stop means the polish proceeds gently at a reasonably low rate without deteriorating topography and only gradually changing sheet resistance when the ultralow-k is exposed. The stack consisted of copper, barrier layer, SiOCH ARC, sacrificial stop layer and ultralow-k. CMP selectivity was adjusted by varying oxidant concentration, pH value, abrasive content and low-k inhibitor concentration. The study showed excellent topography performance by modifying the slurry selectivity with ~400 Å ultralow-k removal rate reduction, with a recovery step that improved Rs by 22%. Sheet resistance was controlled much better when polish pressure was lowered.

Building reliable structures

From a practical standpoint, mechanical reliability is the primary challenge in bringing low-k dielectrics into the device. Because adhesion values can differ drastically between companies depending on the technique used, sometimes it is best to use a known reference. "When no metals are involved, we want the adhesive strength between the films to equal the cohesive strength of the SiCOH film itself," Edelstein said. "The same goes for interfaces between metals. The only time you really can't get that is with the dielectric cap to the copper. So a metal cap would provide an advantage, but so far none of these selective metal capping schemes have proven manufacturable."

Some of the most important low-k material properties include the dielectric constant, Young's Modulus, hardness, coefficient of thermal expansion (in plane and out of plane), film stress, and adhesion to other dielectrics. Surface treatments that help adhesion must be carefully optimized because of the potential to damage underlying films. Wafer warpage is a particular concern for structures built on SOI.1 Managing stress, both throughout the interconnect fab process as well as between the substrate and packaging materials during thermal cycling, is key to device reliability.

The most widely used first-generation low-k material, SiCOH, has advantages including a relatively high dielectric strength (8-9 MV/cm vs. 11 MV/cm for SiO2, 3-4 MV/cm for polymer dielectrics). SiCOH supports only a low concentration of copper atoms in the dielectric, making it fairly resistant to dielectric breakdown. However, this is only true for the dry, bulk film. Once integrated and exposed to plasmas and water, catastrophic copper leakage paths can form. "A plasma damaged or directly polished SiCOH film supports a high copper concentration and is very hydrophilic too, so that combination is bad for copper and can cause a large amount of corrosion of neighboring copper and a large amount of drift of copper ions into damaged regions, which, in turn, could lead to an electrical failure," Edelstein said.

He added that breakdown strength, like the structures themselves, is going to vary depending on the situation. "It's a common misconception that if your nominal dielectric strength is way above your nominal electric field on the chip, then you're OK; you have to be concerned with the tails of the distribution and defects. A minimal space between lines or extra metal can narrow the gap between conductors and make your structure more sensitive to local dielectric strength, even if your nominal value is acceptable."

Maintaining dielectric strength going forward will be particularly challenging because as the industry continues to scale dimensions, the operating voltages are no longer being scaled down, so the electric fields are necessarily increasing with each generation. This puts more burden on fragile low-k dielectrics. This is one reason Edelstein emphasizes zero-damage processing.

"If the material is too weak and all of them have some amount of tensile stress, then in the extreme case they can spontaneously crack due to the thermal mismatch between the metallization and dielectric. The driving force goes as stress squared over the modulus, which is the strain energy release rate, and we want to minimize that component," Edelstein explained. He added that, importantly, there is a misconception that to minimize the strain energy release rate will help with packaging reliability or chip-to-package reliability, but he says this is essentially a different issue. "For packaging, adhesion, cohesive strength and fracture toughness are the core parameters that must be optimized. After that, in the first-generation dielectrics, our low-k materials had a higher fracture strength than silicon, so if you had a crack from dicing and then you packaged the chip, the crack tended to dive into the silicon substrate. And as long as you had a technology that would stop that from happening, you were OK. We're now getting to the point where the fracture toughness of the low-k dielectric is less than that of silicon."

In packaging, many mechanical reliability issues are possible, including bond pad delamination, delamination at the die corner and mold/underfill-induced cracking. Better bond pad designs, such as bond-over-active design rules (also called chip under pad), essentially place the I/O circuitry under the probe region for wirebond pads and BGAs to reduce the die size without transferring stress to the underlying device. Modeling can be effectively used to optimize design rules based on interconnect material limitations (modulus, hardness, coefficient of thermal expansion, stress, and adhesion) and packaging limitations, such as coefficient of thermal expansion and thermal budget.

Finite element modeling (FEM) in a nested fashion is used to model the entire back end. It is important to know the material properties of all materials, including adhesion values, glass transition temperatures, thermal coefficients of expansion, etc. FEM has also been used to examine the chip-package interaction. For instance, FEM has shown that lead-free solder bumps will induce a higher driving force for delamination than eutectic and high-lead solder bumps, and plastic packages and larger die sizes will have a larger driving force than ceramic packages.

One of the ways that packaging has been improved for low-k compatibility is through the development of lower-stress packaging materials. However, one needs to exercise caution with low-stress epoxies because solder ball fatigue can lead to a new failure mechanism — ball cracking. Bond pad deformation can also be controlled by stacking vias through the multiple levels of metal, strategically positioned under the bond pad at specific sites. For a given pad design, this deformation is related to Young's modulus.

Alternative approaches

The lowest-integrated k values achieved to date have been with air gap structures. Though air gap approaches have traditionally been viewed as exotic, they nonetheless are demonstrating feasibility in some multilevel structures. Time will tell whether they will ultimately make it in production devices.

One of the challenges with air gaps is misalignment between the via and underlying wire, resulting in poor coverage of barrier metal at the via bottom. Plating or wet chemical cleaning solutions can enter the air gap areas, leading to failure. At this year's International Interconnect Technology Conference (IITC), Junji Noguchi and colleagues at Hitachi Ltd. (Tokyo) will present a novel air gap structure with underlying via base that prevents via open failures (Fig. 4 ). Air gaps are formed using CF4 plasma etch-back of CVD films. A via over the metal 1 forms a via base on which the metal 2 with interspersed air gaps are built. By eliminating the air gaps directly above the V1, yields can be raised dramatically while still attaining a capacitance reduction up to 32% (k=2.7).2 The air gap structure demonstrated equivalent electromigration and stress-induced voiding behavior, but better TDDB performance because of elimination of a CMP interface.

4. The wire pattern (left) and stacked via chain (right) of four levels of air-gap interconnects. This approach provides a capacitance reduction of 17-32% relative to a conventional damascene scheme. (Source: Hitachi Ltd., IITC 2006)

In a recent study by engineers at Infineon (Dresden, Germany), two metal layers with air gap structures using a close-off processing scheme demonstrated an effective k of 2.3.4 Parameters such as capacitance, leakage current and breakdown voltage of air gap structures were compared with structures without air gaps built on the same wafers. Air gap widths of 380 nm were formed in 0.5 µm wide copper lines with an aspect ratio of 1 using a TEOS-based SiO2 with slight incorporation of nitrogen and k value of 4.2. Silicon nitride and modified TEOS prevents the deposition of ozone TEOS. Nitride etch stop and capping layers were used. An additional lithography step defined the air gaps. A timed etch or buried nitride etch stop defined the depth of the air gaps. Selective ozone TEOS deposition at high pressure and ozone concentration sealed the air gaps. Capacitance reduction between closely spaced lines was up to 50%, and the leakage current density of air gap structures was ~30% higher than that of full structures, which may have been caused by etch damage. Breakdown voltage is lower than that of PECVD oxide, but still higher than that of most low-k dielectrics (5-6 MV/cm). Electromigration lifetimes were comparable to structures with dense oxide dielectric, showing the feasibility of air gap approaches.


Since low-k dielectrics were first included in the International Technology Roadmap for Semiconductors (ITRS), low-k dielectrics have trailed the time at which they were supposed to be implemented in production. The introduction of the 2005 ITRS in December 2005 marked the first time the industry has been aligned with the roadmap regarding low-k. This is because of monumental efforts by engineers from the unit process areas all the way to final packaged device testing.

Possibly a few pioneering companies will pave the way in the aggressive implementation of ultralow-k materials (<2.5) in manufacturing. But for the bulk of the industry, low-k implementation will be gradual: "This is not a sprint but definitely a marathon run," one industry expert called low-k. Nonetheless, just as the 2.9 materials made it for 90 nm, it is quite likely that 2.5 materials will make it for 45 nm for some leading device makers. Making this a cost effective transition is the feat.

  1. C. Goldberg et al., "Integration of a Mechanically Reliable 65 nm Node Technology for Low-k and ULK Interconnects With Various Substrate and Package Types," IEEE International Interconnect Technology Conf., June 2005, p.3.
  2. J. Noguchi et al., "Misalignment-Free Air-Gap (MFAG) Interconnect With Via Base Structure for 45/65 nm Node and Below," to be presented at IEEE IITC, June 2006.
  3. H.H. Kuo et al., "Novel CMP Barrier Slurry for Integrated Porous Low-k Technology of 45 nm Node," to be presented at IEEE IITC, June 2006.
  4. A. Stich et al. "Integration of Air Gaps Based on Selective Ozone/TEOS Deposition Into a Multilayer Metallization Scheme," to be presented at IEEE IITC, June 2006.




2.ULSI Semiconductor Atlas - 'Low-k Dielectric'

By Chih-Hang Tung, George T. T. Sheng, Chih-Yuan Lu, Contributor George T. T. Sheng, Chih-Yuan Lu
Wiley-IEEE, 2003


Ultra Large Scale Integration (ULSI) refers to semiconductor chips with more than 10 million devices per chip. ULSI Semiconductor Technology Atlas uses examples and TEM (Transmission Electron Microscopy) micrographs to explain and illustrate ULSI process technologies and their associated problems.

The first book available on the subject to be illustrated using TEM images, ULSI Semiconductor Technology Atlas is logically divided into four parts:
* Part I includes basic introductions to the ULSI process, device construction analysis, and TEM sample preparation
* Part II focuses on key ULSI modules--ion implantation and defects, dielectrics and isolation structures, silicides/salicides, and metallization
* Part III examines integrated devices, including complete planar DRAM, stacked cell DRAM, and trench cell DRAM, as well as SRAM as examples for process integration and development
* Part IV emphasizes special applications, including TEM in advanced failure analysis, TEM in advanced packaging development and UBM (Under Bump Metallization) studies, and high-resolution TEM in microelectronics


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3.Microchip Fabrication: A Practical Guide to Semiconductor Processing-'Low-k Dielectric'


By Peter Van Zant
Edition: 5, 2004

semiconductor fabrication process from raw materials through shipping the finished, packaged device. Challenging quizzes and review summaries make this the perfect learning guide for technicians in training. * NEW chapter on nanotechnology * NEW sections on 300mm wafer processing * Processes and devices, and Green processing * Every chapter updated to reflect the latest processing techniques


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4.Fundamentals of Semiconductor Manufacturing and Process Control -'Low-k Dielectric'


By Gary S. May, Costas J. Spanos, Contributor Gary S. May


A practical guide to semiconductor manufacturing from process control to yield modeling and experimental design

Fundamentals of Semiconductor Manufacturing and Process Control covers all issues involved in manufacturing microelectronic devices and circuits, including fabrication sequences, process control, experimental design, process modeling, yield modeling, and CIM/CAM systems.

Following an overview of manufacturing and technology, the text explores process monitoring methods, including those that focus on product wafers and those that focus on the equipment used to produce wafers. Next, the text sets forth some fundamentals of statistics and yield modeling, which set the foundation for a detailed discussion of how statistical process control is used to analyze quality and improve yields.,M1

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