Ron@Maltiel-consulting.com Semiconductor & Patent Expert Consulting

IP Litigation expert consultant and patent expert witness for process, device, and circuit of  Dynamic

 Ram (DRAM), Flash  (NAND, NOR, EEPROM), and Static Ram (SRAM) Memories,

 and Microprocessor, Logic, and Analog Devices

EE Times:
Macronix tapping SONOS for next-gen flash

 
SHANGHAI, China — Memory maker Macronix International is working on a new Flash structure that will help break down barriers faced by today's floating gate technology when it scales to the 45 nanometer node.

The structure, called BE-SONOS, is a variation on the silicon-oxide-nitride-oxide-silicon formula that has been around for years and is currently being pursued by other companies such as Motorola Corp. and Cypress Semiconductor as a better means for embedding flash than the typical floating-gate structure.

Allen Yu, a researcher at the Macronix Technology Development Center, said the company will produce a 2 gigabit test chip next year using 75-nanometer technology. He thinks commercialization will take place at 45-nanometer, sometime around 2010, once floating gate NAND has reached its scaling limits. Macronix plans to manufacture the chips as well as license the technology.

Because the SONOS structure is compatible with a generic logic process, it could help push embedded flash into applications long considered out of bounds because of cost, such as SoCs for consumer electronics.

Yet one of the key problems afflicting SONOS is its leakage. In most cases, the first oxide layer is too thin to prevent tunneling. In the past, researchers have tried to solve this by adding an extra layer of nitride, for a total thickness of less than 4 nanometers. This resulted in better retention, but the trade-off was slower programming times.

In its Bandgap Engineered SONOS, Macronix has introduced a SONONOS structure. "The innovative part of BE-SONOS is to replace the tunneling oxide (O1) in SONOS with O1-N1-O2, so BE-SONOS equals a SONONOS structure," Yu said. The result is a thicker dielectric layer, measuring 5.3 nanometers. That is then overlaid with a 7-nanometer nitride layer (N2) that traps the charge. The final layer (O3) is a 9-nanometer thick blocking oxide.

Because of the total thickness of the first O1-N1-O2 layer, retention is high. But when the device is programmed, band offset happens, which effectively eliminates the blocking properties of N1 and O2, allowing the electrons to easily tunnel through the O1 layer.

Yu said the structure is suitable for NAND or NOR flash, but will probably first be used in NAND. Programming happens at 6Mbytes per second, but erase times are 3 to 4 milliseconds per block, a little higher than the normal 2 milliseconds, so the company is working to fine tune it. Endurance is on par with today's flash at 10,000 or more cycles.

Samsung recently introduced a similar structure called charge-trap flash (CTF). Its CTF-based NAND chip should be more reliable than traditional flash because it reduces cell-to-cell interference that can make bits harder to read.

There is a key difference between the two approaches, though. Samsung refers to its structure as TANOS, which comprises tantalum (a metal), aluminum oxide (a high-k material), nitride, oxide and silicon layers. Using a TANOS structure marks the first application of a metal layer coupled with a high-k material in a NAND device, Samsung said.

BE-SONOS is another type of charge trapping device, but it could be more straight-forward to produce. "TANOS adopts new materials and a new process, but BE-SONOS is fully CMOS compatible, so it is easier to mass produce," Yu said.