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Low-k Bursts Into the Mainstream...Incrementally                                              
At a Glance
Although viewed as an eventual necessity, the industry has so far successfully restricted low-k integration through workarounds. Issues of porosity, mechanical integrity and processing, though serious, are not unsolvable; however, the financial burden of retooling a fab every 18 months to two years has limited adoption to those applications where low-k is essential to make the device function.
Creating Manufacturable Ultralow-k Dielectrics

Years back, a TV commercial promised, "We will sell no wine before its time." A paraphrase of this might pledge, "We will integrate no low-k before its time." So far, designers have come up with one workaround after another to avoid using low-k materials in their devices, but options are starting to run thin (Fig. 1 ).
Farhad Moghadam, senior vice president and general manager, thin films product business group and corporate foundation engineering at Applied Materials (Santa Clara, Calif.), stated that at 90 and 65 nm, most manufacturers will use carbon-doped oxide (CDO) low-k materials based on a mainstream application, noting that major low-k integration issues have been resolved with good mechanical properties, such as the Intel Pentium and AMD Athlon processors, which incorporate low-k material at multiple levels.
With regard to next-generation low-k materials, advances are being made by pore engineering of low-k films. However, the integration of future, more porous low-k materials requires improvements to mechanical, thermal and chemical properties, and these are being addressed with post-deposition cure approaches.

1. To avoid process changes and expensive retooling, the semiconductor industry has postponed the implementation of low-k materials through the application of ingenious workarounds. How well this has worked can be seen in the alteration over the years of the ITRS’s predictions. (Source: Dow Corning)

Foundry acceptance has not been enthusiastic; 130 nm works, and switching to 90 nm is expensive. Many cannot afford it without a high-volume product. Knowing how to go from 90 to 65 nm using new low-k materials is one thing; whether results justify it is another. With effort and expense, 2.0 is possible, but with an effective dielectric (keff) of 2.5, the gain is dubious. Currently, at 90 nm, deposited low-k material typically has a keff of 3.0 to 2.9. Its properties are similar to SiO2's, and after integration with a block layer, the keff drops to the 3.2 to 3.1 range.

No technical roadblocks to low-k adoption exist for current production technology. Besides, it is not used for every layer. To meet packaging needs, the top two layers typically use FSG or USG, providing the necessary hardness to meet mechanical requirements. For advanced applications, a flip-chip configuration using solder bumps can be used, which is more tolerant to low-k materials.

Current issues are how to strip resist without low-k damage and — when etching porous or semiporous low-k material after forming the via or trench — how to seal the pores etched open. So far, there are no satisfactory solutions. One possibility is doing all these in situ, inside the dielectric etch chamber. Applied is researching chemistries and process regimes gentle to low-k materials that still do a good resist strip with no visible imperfection. It remains to be seen whether the process provides the necessary electrical perfection.

Keith Buchanan, business development manager for 300 mm products at Trikon Technologies (Newport, South Wales, UK), pointed out that, while there are many candidate low-k materials, it has proven impossible to integrate porous materials into multilevel copper interconnects without mechanical damage and increased keff. "Maintenance of the keff is increasingly difficult as the metal pitch is reduced; etch/ash damage becomes more significant, and the pore-sealing layers increase the keff even more." Buchanan added it might make more sense to stick with a denser material and higher keff, which is what device manufacturers are doing.

Integration and porosity

Whether low-k is porous or not is not the point. As Tominori Yoshida, PECVD business unit manager for ASM (Phoenix), pointed out, "SiOC-type low-k materials, such as ASM's Aurora 2.7 and Aurora ULK, are porous. Pore size is the point — the pore's density and its connectivity."

Tom Baum, R&D vice president at ATMI (Danbury, Conn.), views a plasma-enhanced CVD-type approach as state-of-the-art for low-k films' deposition. Different OEMs have aligned with specific chemistries — Black Diamond and Coral, for example — and there is some toolset and related chemistry segmentation in the marketplace.

Ravi Laxman, ATMI's director of technology for advanced materials, indicated that at keff=2.8, most precursors produce low-k films in the same k range area with similar silicon-to-carbon ratios and densities. At k<2.5, chemistries will be different, and as 2.0 is approached, more materials will be available. At 90 and 65 nm, use of k values of 3.0 to 2.8 will continue. With high-performance 65 nm, new precursors will appear to develop 2.5 and 2.4.

Integration centers on the low-k film's mechanical properties. Improved hardness and modulus are desirable because, when building a multilayered stack and doing sequential processing, films go through chemical mechanical planarization (CMP). Porosity is increasingly considered for the 45 nm node; however, porous low-k requires the pores to be sealed to keep out contaminants, which raises the k value.

Adopting porous low-k while moving to thin barriers will not be easy. CVD and atomic layer deposition (ALD) are being considered for 45 or 32 nm. Film hardness is important, because fabricating device structures at those nodes thins dielectric films. Maintaining small pore size and density to harden the film will be critical. Some still sandwich low-k materials using SiO2. This approach may still be used at 32 nm, where it would be possible to have different low-k levels (3.0 and 2.8 to 2.0) at various levels. Some are taking a hybrid approach, mostly a spin-on and CVD film, but there could be CVD film hybrids that provide both a lower k and then a higher k in combination.

Phil Dembowski, global market manager for semiconductor materials at Dow Corning (Midland, Mich.), points out that most manufacturers going into 90 nm production — certainly logic, not DRAM — are using low-k CVD materials, and CVD precursor use is up.

At 90 nm, CVD SiCOH films were chosen almost universally, instead of going the spin-on route. Dow Corning believes few will use spin-on at 90 nm. Most prefer to extend what is being used to 65 nm. Some changes are unavoidable; for example, replacing cobalt silicide with nickel silicide or going from regular gate to high-k gate dielectrics. If a new dielectric gives a 10% performance improvement with a 3% yield loss, the tradeoff is not worthwhile and a workaround is pursued. The 45 nm node may require so-called ultralow-k (≤2.5). However, many will probably continue to use the k=2.9 to 2.7 CVD films already here.

Tatsumi Mizutani, chief engineer at Hitachi High-Technologies' etching process design department (Kudamatsu, Japan), pointed out that non-porous low-k (~3.0) materials are widely used at 90 nm. "I believe ultralow-k (~2.0) will be unavoidable at 45 nm," he said, adding that reliability issues would have to be solved first.

The issue is no longer k value. Getting a 2.0 or 1.6 dielectric is easy. What is difficult is getting a k of 2.3 and mechanical properties with a modulus above 6 or 8 GPa, considering that SiO2 has an elastic modulus of 73 GPa.

"From a CMP perspective, CVD materials rule. CDOs — carbon doped oxides — are preferred, although there was talk about using a CDO material and no other layers," said Rich Baker, vice president of slurry technology at Rohm and Haas Electronic Materials, CMP technologies (Woburn, Mass.). He added that then the TEOS cap was used to solve post-CMP cleaning and etch problems. "A TEOS or FSG cap in some instances — where you stop and leave 200 Å of the cap — is pretty much where most are at 90 nm."

At 65 nm, work proceeds on systems still using TEOS hard masks, to remove them and stop on the CDO material. CVD dielectrics with some additional processing seem like a solution. However, the TEOS hard mask must be cleared while retaining CDO topography control.

Porosity and density

Wilbert van den Hoek, CTO at Novellus Systems (San Jose), noted that leading players are at 90 nm, with some starting on 65 nm. "Mainstream, for both nodes, it'll be a ~3.0 keff film. After figuring out how to make these films work at 90 nm, nobody wants to redo all their integration work for the minor gains a k=2.7 film would offer for the 65 nm node," he said.

Low-k films with k values of 2.7 and above are considered "dense" films, and at 2.5 and below, "porous" (Fig. 2 ). With porous films, the question is whether the pores are connected — open — or not connected — closed. The former require a complete new integration scheme compared to "dense" films. However, careful analysis of the present-generation 2.7-3.0 PECVD OSG films shows that these films are porous, having closed pores with a diameter in the range of 1-1.5 nm. Developments in the deposition of PECVD 2.2-2.5 films resulted in films with a similar closed-pore structure, compared with the 2.7-3.0 PECVD OSG films. The density of these pores has been increased to achieve the lower k values. Post-process UV-assisted thermal processing is used to offset the degradation in mechanical properties resulting from increased pore density.

2. Any low-k film that has a value of 2.7 and above is considered to be dense, and 2.5 and below, porous. Current-generation 2.7-3.0 PECVD OSG films have closed pores. PECVD developments have resulted in 2.2-2.5 films with similar closed pore structures, but of higher density, which enables them to achieve lower k values at 5.1 keV (370 nm). (Source: Novellus)

The problem with connected pores is that when the barrier is laid — typically an ALD barrier at 45 nm — it diffuses into the low-k material through the pores, clogging them, metallizing the dielectric and shorting out everything. Thus, either pore sealing or a closed cell dielectric material that does not require sealing is needed. Values of ~2.0 or below are necessary for pore sealing to provide a benefit over a 2.7 low-k "dense" material. To seal a 14 Å pore, ~30 Å of sealant are needed. That is 3 nm on each side, so 6 nm out of the 60 nm space is a 4.0 "high-k" material, offsetting the benefit of having the bulk low-k go down from 3.0 to 2.4.

Novellus developed a two-precursor PECVD process. The precursor used to make a 3.0 film is mixed with a second one — a pure organic molecule — and incorporated unaltered into the film; the OSG network grows around these molecules. When the organic molecule is removed, more uniformly distributed pores are created than would result from a single-step process.

A UV lightsource is used to remove organic molecules, tuned to match its wavelength to the strength of the molecule's bonds. That cracks the organic molecule into methane-type byproducts, which at an elevated temperature (350-400°C) diffuse through the low-k film, leaving it. This results in no pore interconnectivity and improved mechanical properties.

Sorting out choices

Michael Mills, director of emerging technology for Advanced Electronic Materials at Dow Chemical, observed that those setting the standard of what will work at 65 nm — as well as past 45 and 32 nm — stand behind a hybrid interlayer dielectric (ILD) structure to address integration issues that cannot be mastered in a monolithic or homogeneous manner.

CVD monolithic homogeneous trail followers, such as Toshiba and Sony, realized that because of integration limitations (specifically etch control at the trench bottom with CVD OSG materials), there were no workable solutions for 65, let alone 45 nm, and turned to hybrid low-k. This is not revolutionary; Fujitsu was the first to put true low-k into mass production back in 2000 at the 130 nm node, using SiLK and SiO2 as a hybrid ILD. The combination of an organic and an inorganic low-k solves 50-60% of integration headaches. SiLK's perspective to be the only true low-k ILD material to be commercially used at 130, 90, 65 and 45 nm is good, particularly since the second-generation porous SiLK material integrates identically.

Paul Apen, program manager at Honeywell Electronic Materials (Sunnyvale, Calif.), believes k values for 90 and 65 nm processes will be in the high twos: 2.9 or 2.7. At 45 nm, device makers would incrementally consider increased porosity or compositions that lower the ILD material's dielectric constant to 2.5 or 2.4. The question is integration, because they all present unique difficulties, even when going from 3.0 to 2.7 or 2.7 to 2.5.

"Low-k introduction has slipped to 65 nm for the first pilot-line-type introduction, which will be more of a ramp for 45 nm," said Eric Johnson, COO of JSR Micro (Sunnyvale, Calif.). There has been a sluggish approach in implementing low-k dielectrics, and it has been primarily CVD-based materials, partly because it is familiar and partly because no one feels any great pressure to move to lower-k material. However, this is not a materials question, but instead an integration question. CVD has made inroads and products are being put out using it. Until there is enough pressure to push low-k to the ultralow-k level, engineers will not take chances with their process development.

The cleaning question

"To meet needed propagation delays, it was expected that copper resistivity could be maintained at near bulk levels, and interline capacitance could be gradually reduced for each technology node," said Ivan Berry, director of technology at Axcelis Technologies (Beverly, Mass.).

Unfortunately, copper resistivity increases when confined into narrow lines during the damascene process, caused by increased surface and grain boundary scattering. Also, integration hurdles with low-k-value materials kept real capacitance from dropping as hoped. Often, keff increases as dielectric k value decreases because of the added films needed to overcome lower-k materials' deficiencies and plasma processing damage to dielectrics. Axcelis has focused on reducing keff without resorting to very porous dielectrics. They are trying to reduce parasitic damage issues, as well as facilitate thinner film use by improving adhesion, barrier integration, and dielectric breakdown.

Low-k metrology

With product wafers having a four- or five-layer stack, multilayer stack measurement has become critical, but the measurements themselves have grown complicated, said Murali Narasimhan, senior director of marketing, films and surface technology division, at KLA-Tencor (San Jose). This benefits spectroscopic ellipsometry (SE) because it uses multiple wavelengths, generating more information than reflectometry, which has difficulty measuring multilayer stacks. SE enables the simultaneous measurement of the multilayer stack's thickness and refractive index.

Engineers use a copper pad underneath each layer to reflect off a particular stack, instead of looking at the entire stack of multiple ILD layers, to isolate the measurement for a specific stack. However, there are CMP dishing issues associated with blank copper pads, which can create depth of focus problems with lithography and defectivity control.

When broken into gratings, these copper pads are more robust to CMP processing. However, because a grating introduces unwanted noise in the optical spectrum, the metrology must measure on top. KLA is producing algorithms to allow multilayer film thickness and refractive index measurements on top of these gratings — what they call "dielectric pattern metrology." These measurements will focus on the die, instead of doing a proxy measurement at the scribe line, as is done at 90 nm. The 65 and 45 nm nodes will have extensions to these algorithms, enabling them to operate on 3-D features.

The need for electrical monitoring has increased, because a function of low-k is reducing overall RC delays; however, controlling these materials' dielectric constant is hard because they are sensitive to subsequent processes — plasma or etch steps — requiring an in-line way to electrically monitor dielectric constant and leakage. Corona oxide semiconductor-based tools can monitor electrical properties, enabling inline measurements of the dielectric constant, plasma damage, leakage or soft breakdown.

The mechanical properties of low-k films can be characterized by surface acoustic wave (SAW) technology, said Michael Gostein, chief technologist at Philips AMS (Natick, Mass.). An issue with porosity is its effect on stiffness. SAW technology can characterize stiffness perpendicularly and parallel to the film's plane, differentiating between those two components — the film's anisotropy. Non-porous films are isotropic, so the stiffness is identical in both directions.

In porous films, stiffness becomes anisotropic and the film is stiffer in plane than out of the plane. For CMP, in-plane stiffness may be more important; for packaging, the opposite is true. A technique that characterizes this factor for different porous films can be useful, particularly with a mapping capability for low-k's uniformity patterns across the wafer. FTIR offers additional capabilities to view low-k's emerging properties, by permitting analysis of chemical composition. IR is now on automated 300 mm platforms, with pattern recognition, optics and algorithms tailored for product applications, and is ready for online measurements.

The progression to smaller architectures has followed an evolutionary track. At 45 nm, performance advantages will not be realized with current integration schemes. Ultralow-k materials will be necessary just to maintain breakeven speed if linewidths are scaled, and performance will not be enhanced without additional design work and layers.

Fabs can no longer meet Moore's Law by entirely retooling every 18 months. With the tremendous investment in capital equipment, the fab's outlook is pragmatic — avoid quantum jumps — and this trumps the perceived value and possible applications of increasingly lower k values. Economics, not technology, now dictate the course.


Creating Manufacturable Ultralow-k Dielectrics

Derek Witty, senior director, Blanket Dielectric Film Group, Applied Materials, Santa Clara, Calif.

Although k-material adoption was relatively slow because of integration challenges, especially in the packaging area, today interlayer dielectric films with k values in the 3.0 range have been successfully integrated into the 90 and 65 nm technology nodes with mechanical strengths capable of withstanding the packaging process. However, lowering the dielectric constant to meet the needs of the 45 and 32 nm technology generations will result in materials of even less hardness. Films with k values in the range of 2.7 to 2.5 that can meet the mechanical strength requirements associated with packaging will need to be developed.

New CVD approaches are being pursued to create films with k values of 2.5 and lower. In first-generation low-k materials (k≥3.0), carbon doping of silicon oxide is the standard approach. Although carbon doping of silicon oxide effectively lowers k value, the film's hardness and elastic modulus are also reduced. Further carbon doping to achieve a k value of 2.5 results in a film with a mechanical strength impractical for packaging integration. An alternative solution is to introduce nanopores into carbon-doped oxide (CDO).1 The incorporation of porosity enables further k value reduction down to 2.0.

Using conventional PECVD technology, this method involves co-depositing a heterogeneous CDO/organic material that is then post-cured to drive off the thermally unstable organic species, leaving uniformly distributed pores of <2 nm diameter throughout the film.2 Pores of this scale are critical in preventing metallization barrier layer penetration. With ALD anticipated to be the means of barrier deposition for future geometries, penetration poses a significant integration challenge. Films created using this approach show excellent resistance to barrier intrusion, even without pore sealing.

Because of its high efficiency, UV light or e-beam curing is superior to furnace curing. As the film is cured with UV or e-beam to create the homogeneous nanopores, cross-linking of the silicon oxide matrix also occurs. This improves the film's hardness and elastic modulus (~1 and 5.8 GPa, respectively, post-treatment).3 The mechanical strengthening of the film during the cure is critical to enable integration, particularly during CMP and packaging. We have evaluated films of k=2.5 with pore sizes <10 radius and densities of 1.1-1.25 g/cm3 and demonstrated successful integration. Back-end-of-line electrical results confirm successful performance of a film with k value of 2.5.

1. R.P. Mandal et al., U.S. Patent 6,171,945, 2001.
2. R.P. Mandal et al., U.S. Patent 6,451,367, 2003.
3. G. Dixit et al., "Film Properties and Integration Performance on a Nano-Porous Carbon Doped Oxide," IITC, 2004.