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INDUSTRY NEWS

Chipworks Corner

TSMC fabbed Matrix 3-D memory array
with unique 0.15-m, seven-metal process

With the incredible growth seen in the hottest memory segment, 2005 could have been dubbed the “Year of Flash.” Big demand spikes in consumer products such as MP3 players, cell phones, and digital cameras largely caused the prodigious increases in the flash-memory market. NAND flash prices have been dropping to commodity levels, but they are still not low enough for children’s toys and some other markets.

However, other programmable memory technologies have been lurking in the background, also aimed at consumer product uses. For example, Matrix Memory developed a three-dimensional, antifuse-based, one-time-programmable memory, targeted at prerecorded applications such as game cartridges and digital music albums.

In a classic Silicon Valley story, Matrix developed the technology at Stanford, prototyped and “productionized” it at Cypress Semiconductor’s Silicon Valley Technology Center, and started volume manufacturing at TSMC. The company launched the first samples in 2003. Mattel, Disney, and other companies adopted the technology before Sandisk acquired Matrix earlier this year. (Mattel used the Matrix memory for video and music cartridges for their ill-fated Juice Box media player.)

Since it was an alternative technology, Chipworks analyzed some of the Matrix devices and found that they were very different from any of the other one-time memories on the market. The subject of the analysis was a JuiceWare 16-Mbyte (128-Mb) cartridge with a “Dexter’s Laboratory” cartoon on it. Inside the cartridge, the chip was put together in an Amkor 32-pin thin small outline package. The die size was 33 mm2, which compares quite favorably with the 22 mm2 of a competitive 64-Mb NOR ROM that was analyzed at the same time.

Figure 1 shows the die delayered to metal 1. A 10 16 array of memory blocks on the die can be seen clearly. Each of these is 1024 1024 bits, so given the two layers of memory, there are actually ~320 Mb (40 Mbyte) of storage in this chip, much more than the 16 Mbyte indicated on the bubblepack that the cartridge came in.

Figure 1

TSMC fabricated the chip in a variant of its 0.15-m process using seven metals, including six levels of tungsten metal and a top level of aluminum-based metallization. It features 0.15-m minimum-gate-length NMOS and PMOS transistors with cobalt-silicided polysilicon gates and source/drain diffusions. The use of a dual gate-oxide process allows for high-voltage programming transistors. Two layers of polysilicon-based antifuse diode structures—between metal 3 and 4 and between metal 5 and 6—form the elements of the 3-D memory array. The metal 1 and 2 levels are used for the CMOS circuitry.

The memory cell size is 0.11 m2, effectively 0.055 m2/bit with the two layers. With the 0.15-m minimum feature size, this provides a cell metric of 2.4 F2—which compares with 15 F2 in the 0.15-m NOR ROM mentioned earlier.

Taking a look at the cell structure itself, Figure 2 shows a schematic of a pair of cells, sectioned along a wordline. The storage element consists of a PIN diode formed in a polysilicon pillar, with a thin antifuse oxide layer underneath the wordline. The cell is programmed by applying high voltage to the wordline and holding the bitline at ground. This breaks down the oxide layer and shorts the diode to the wordline. The PIN structure seems to be used to provide a voltage drop across the diode in unselected cells, protecting the oxide during programming; it also allows the use of a thinner oxide, increasing programming speed.

Figure 2

The SEM image in Figure 3 reveals both layers of the cell stack sectioned along the bitlines. A stain sensitive to doping was used, so the P+ and N+ layers at the tops and bases of the pillars can be seen. Figure 4 shows a TEM image of three cells (wordline section), and Figure 5 is a close-up of the ~2.5-nm antifuse oxide. The bitlines and wordlines are tungsten on titanium nitride (TiN); the bitlines (bottom) have a TiN cap, with the polysilicon diode pillars rising up to the wordline. The scanning capacitance image in Figure 6 shows the differential doping of the pillars (the purple P-doped layer is above the yellow N-doped layer, and the mottled features are the tungsten metal).

Figure 3
Figure 4
Figure 5
Figure 6

The process sequence seems to be:

1. Deposit and define the W/TiN bitlines.

2. Gap-fill with oxide and planarize to expose the tungsten.

3. Deposit the TiN cap, followed by in situ N-doped polysilicon (~100 nm), which changes to undoped poly.

4. Mask and etch the poly + TiN into pillars.

5. Deposit oxide to cover the pillars, and polish them back to expose the undoped poly.

6. Implant boron into the pillar tops.

7. Grow the antifuse oxide.

8. Deposit and define W/TiN wordlines.

While using conventional processing steps, this sequence must be a deviation from the process modules normally used by a foundry such as TSMC. This raises questions about the pricing, and whether the parts were actually cheap enough for Matrix to take the technology into the low-end market in sufficient volume to generate a real financial return.

Since Sandisk has bought the technology, it is a moot point: as an IDM with its own fabs, it can dedicate the space needed. These days Sandisk is positioning itself as a content and solution supplier rather than as a component supplier, as witnessed by its recent launch of a Rolling Stones album on a flash card. The combination of Sandisk muscle plus Matrix technology could become a market leader.—Dick James

This report is one of a regular series of device-level process analyses, written exclusively for MICRO by Chipworks’ senior technology adviser, Dick James, a 30-year veteran of the semiconductor industry. Chipworks is an Ottawa, Canada–based specialty reverse engineering company that gets inside technology and takes apart ICs and electronics systems in order to provide engineering information for its customers. The technical intelligence customers are usually within manufacturing companies, performing product development, or doing strategic marketing or benchmarking studies. The patent intelligence clients are usually patent lawyers or intellectual property groups within manufacturing companies.