Ron@Maltiel-consulting.com Semiconductor & Patent Expert Consulting

                          Litigation expert consultant and patent expert witness for process, device, and circuit of Dynamic

 Ram (DRAM), Flash  (NAND, NOR, EEPROM), and Static Ram (SRAM) Memories,

 and Microprocessor, Logic, and Analog Devices.

 

Integrating NAND flash memory in a system

_____________________________________________________________________________________________________________

  

Yuping Chung (Silicon Storage Technology) / EETimes

(08/15/2008 7:00 PM EDT)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=210003539

 

A variety of NAND flash architectures, the constant migration to newer, more advanced process technologies, and the continual introduction of new features have converged to make the design of NAND flash memory subsystems more challenging than ever.

The current situation in the NAND flash market presents designers with three options. They can build their own discrete solutions using flash controllers and separate NAND devices. They can use embedded NAND controllers (within chipsets/processors) along with separate NAND devices. Or they can opt to buy managed NAND solutions that offer the entire NAND memory subsystem in a pre-packaged solution.

The expansion of the NAND flash market has attracted a variety of suppliers, each offering its own technology advances. For example, as device densities passed 4 Gbit, NAND flash manufacturers found the traditional 512-byte programming page no longer offered an optimal segmentation for programming. Many suppliers instead moved to a 2-Kbyte page size. More recently, manufacturers started shipping a larger 4-Kbyte page size in volume. Furthermore, 8-Kbyte page size is now being offered in latest 40nm technology. At the same time, in an attempt to increase capacity, manufacturers have moved from single-level cell (SLC) to multi-level cell (MLC) architectures, which store as many as 4 bits per cell. Further complicating the problem, competing flash memory IC suppliers are constantly adding new functionality such as read caches, write caches, copy back and multi-plane programming functionality. While these new features and architectural enhancements were intended to improve performance, they present inherent compatibility problems for OEMs looking to minimize inventory risk by sourcing NAND flash from multiple suppliers. Incompatibility issues also arise because of the fact that NAND flash from different vendors may have different erase and program timing requirements.

NAND controllers addressed this problem by offering a simple, standardized interface between the host system and a block of flash memory regardless of the source. In a discrete solution, OEMs typically purchase controllers and NAND memory ICs from different suppliers and then mount the devices on a board. Once the system powers up, a flash file system in the controller recognizes the memory devices, executes all necessary handshaking routines for flash media support and performs low-level formatting.

More recently, vendors have begun to address this issue by offering managed NAND solutions that take simplicity of design to another level by combining an integrated ATA controller with one or more NAND flash die in a multi-chip package. Offering a complete plug-and-play NAND storage solution in a compact package, this approach offers attractive cost and space savings and has proved highly popular in embedded applications using the standard ATA/IDE protocol.

Both discrete and managed NAND solutions use a microcontroller (MCU) to decode all host commands and translate them into flash commands. To boost performance the MCU is usually supported by a small SRAM buffer between the host and flash devices. To eliminate any latency that may occur due to MCU overhead, these solutions typically use a DMA block to interface between the MCU and the data channel running between the host ATA IDE bus and the flash memory. The DMA block moves the data between the SRAM buffer and the flash memory to reduce MCU overhead.

The key differentiator in any NAND flash subsystem, whether it is a managed or discrete design, is the embedded flash file system, which manages the handshake mechanism between the host and the flash memory. From the designer's point of view, this capability dramatically simplifies the task of writing data to memory by automatically compensating for many of the unique architectural differences between flash devices from different suppliers, such as error correction requirements, page size or number of bits per cell. It also can be used to store unique customer-specific features or add bug fixes when required. Finally, the flash file system also typically holds a number of important media management functions that help ensure data integrity and a longer life for the NAND flash memory subsystem.

Not all implementations of the flash file system are the same, however. Many controllers implement the flash file system in a lower cost, mask-programmable ROM. Controllers from other vendors, such as SST, use an in-circuit reprogrammable flash memory to perform this task. Given the rapid rate of change in NAND technology, this distinction is crucial. Designers using a controller that stores firmware in ROM must generate a time-consuming and expensive mask change to reprogram the device every time they need to update the firmware. This problem also applies to SoCs with integrated NAND controllers. Inevitably designers using these devices cannot keep up with the large number of changes occurring in NAND memory IC design and must therefore limit their component selection. Designers using controllers that store their firmware in embedded flash, on the other hand, can quickly and inexpensively modify their device as flash memory vendors introduce new features. This capability gives system designers more flexibility to design their memory subsystem by using components from a wider selection of vendors for fast time-to-market, best availability and cost effectiveness.

Key features

Whether a designer is planning on using a managed or discrete approach, he or she should look for a number of key features to ensure maximum performance, NAND memory IC endurance and data integrity. One key feature is embedded error correction code (ECC) circuitry. Random read errors commonly occur when using NAND flash because of errors caused by read/write operations performed on adjacent cells. ECC circuits combat this problem by checking and correcting the accuracy of data as it passes in and out of memory.

This capability has become increasingly important in recent years as NAND manufacturers have turned to MLC techniques to boost IC memory density. Memory manufacturers typically specify one bit random error for every 512-byte in SLC devices. But as manufacturers have moved to denser MLC architectures, their NAND ICs can have up to 4 bit random errors per each 512-byte. Typically an MLC device operates at the same voltage as comparable SLC NAND devices, so each level in a MLC cell has less charge associated with it. As a result, it is more prone to temperature variations. Eventually temperature variations could result in a level change leading to soft errors. In addition, as NAND vendors migrate to the more advanced and smaller process geometry, a powerful ECC engine becomes even more critical. To compensate for these higher error rates, NAND flash subsystems must provide more powerful ECC engines. Some, such as SST's discrete controller and NANDrive product lines, now offer an 8-bit hardware ECC engine which is required by most NAND with 40nm technology.

Bad block management is another important feature in any NAND memory subsystem. While NOR flash memory guarantees the integrity of all memory bits, NAND devices are designed to operate with bad blocks in order to achieve high yield in production. Memory IC manufacturers typically specify which blocks are bad in their devices. At initialization firmware-based bad block management functions identify the location of these bad blocks and automatically map them out of the memory array. The firmware then instructs the controller not to use those specified blocks for storage. If any additional bad blocks are discovered as the memory is used, the firmware updates the bad block maps.

Endurance levels

Endurance presents another issue for designers building flash memory subsystems. Every flash memory IC is subject to write endurance limitations. After repeated erase and program cycles, the memory no longer retains data. As memory manufacturers have moved to smaller silicon geometries and multi-level cells, endurance levels have dropped. For instance, while memory IC manufacturers specified their SLC devices at 100K cycles, newer MLC devices are now specified at only 10K cycles.

Flash memory controllers compensate for this limitation by incorporating complex wear-leveling functions in their firmware. These algorithms track memory usage by block, or page, by matching an age counter that is incremented with each write cycle to a map of the logical and physical sectors on the flash media. Wear-leveling algorithms extend memory IC endurance by automatically instructing the controller to rotate memory writes to blocks with less usage. This function allows the controller to maximize memory IC endurance by ensuring all sectors in a flash IC reach their write limit at the same time.

It also provides a mechanism for alerting the user when media is reaching its endurance limit, which can help prevent the loss of data.

Power conservation is also a key concern, particularly since many NAND memory solutions are used in battery-powered portable applications. To maximize power efficiency, both managed and discrete NAND flash solutions typically feature a power management unit (PMU), which scans the memory subsystem and powers down any inactive functions. When a function is needed, the controller will activate the function instantly and start accessing data from the host.