|45 to 32 nm: Another Evolutionary Transition
by Laura Peters Senior Editor -- Semiconductor International,
Those expecting more revolutionary changes at the 32 nm
node may be disappointed by the evolutionary changes in process
technology that still allow performance specifications of the latest
devices to be met. Still, there are a few notable exceptions.
Like the 45 nm generation, the 32 nm node will take advantage of
the performance tricks of the prior technology generation, including
immersion lithography, multiple stressors for mobility enhancement
and porous low-k materials in the interconnect. The biggest change
at 32 nm will be the introduction of high-k dielectrics and metal
gates into production, though different approaches are likely to be
taken. Other highlights are copper plugs and 3-D integration. This
article will discuss these exceptions to the rule.
Lithography at 32 nm
Although there is no consensus on the chosen lithography
technique for 32 nm, it seems clear that most parties are banking on
the extension of ArF immersion lithography or double patterning,
since extreme ultraviolet (EUV, 13 nm) is unlikely to be ready in
time. The most aggressive geometry shrinks are taking place in the
NAND flash segment, followed closely by DRAM and then
high-performance logic devices (Figures 1 and 2). Flash devices are
characterized by the densest pitches, so the strongest resolution
enhancement techniques (RETs) are typically used. In some ways,
flash manufacturers have become the drivers of advanced lithography
techniques, since they will be the first to incorporate them.
Most companies will introduce immersion lithography at the 45 nm
node. As this issue was going to print, AMD (Sunnyvale, Calif.) and
IBM (Yorktown Heights, N.Y.) announced that they had successfully
completed their development work on the first-generation immersion
lithography process using water, and that the yields on the new
immersion tool were equivalent to those attained using dry ArF
lithography. This is very significant, since it is early evidence
that immersion lithography is likely to work in production and, just
as importantly, will be delivered in time for 45 nm. According to
Nick Kepler, vice president of logic technology development at AMD,
much of the success can be attributed to its close R&D alliance with
IBM, work performed with ASML (Veldhoven, Netherlands), and access
to one of the first immersion tools at Albany Nanotech (Albany,
N.Y.). Paul Agnello, project manager for 45 nm CMOS device and
integration at IBM, stated that the most significant defects - air
bubbles and wafer drying spots - had been taken care of. This
advancement is part of the reason AMD will be able to ramp to 45 nm
six months ahead of schedule, according to Kepler.
Figure 1. Because of accelerations in
cell-size scaling, NAND flash has surpassed DRAM as the most
The rapid progress in immersion lithography means that companies
will make every effort to extend its use to the next generation.
With water and the latest lenses, a numerical aperture (NA) of 1.35
can be attained. The lithography options at 32 nm involve immersion
lithography and EUV (Table 1). However, since the usable range of k1
in manufacturing starts at 0.25, water immersion will not meet all
of the critical-level needs without resorting to pitch relaxation or
double patterning. The next logical step, a change to
next-generation immersion fluids (1.65 refractive index, [RI]) and
higher final lens RI (1.9 from the current 1.57), will enable
minimum resolutions of 39 and 35 nm, respectively (k1=0.28).
The latter would provide an NA of 1.55. However, this infrastructure
is not likely to be in place in time to pattern 32 nm half-pitch
features, so double patterning will become the bridge technology.1
The key challenges here are the overlay requirement and process
integration (see "Lith
Experts Explore Options for 32 nm Half-Pitch").
Figure 2. The different imaging
requirements of leading-edge devices. (Source: ASML)
Franklin Kalk, chief technology officer of Toppan Photomasks
(Round Rock, Texas), said that some of the integration work will be
a challenge for immersion, such as refreshing and recycling the
water, which will become especially critical for much more costly
next-generation fluids. He also said that problems, such as haze
defects (molecular contamination on the mask surface), will be just
as big a problem for immersion ArF as for dry.
These schemes could compete with EUV lithography at the 32 nm
node, but will more likely face-off against EUV at the 22 nm node.
The challenges for EUV include source power, optics lifetime, resist
infrastructure and mask infrastructure.
Last year at this time, we showed how various stressor techniques
will be used at the 45 nm node to improve the mobility of charge
carriers in the channel (electrons in nFETs and holes in pFETs).2
Compressive strain is induced in pFETs using epitaxially grown
silicon germanium (SiGe) in the source/drain (S/D) regions and/or a
compressively stressed nitride layer over the gate. A technique
called stress memorization uses poly implants and a stress transfer
film that is annealed and removed, leaving a memorized strain.
Tensile strain in nFETs is accomplished using increasingly strained
nitride caps. Since then, although biaxial, global strain approaches
on bulk substrates have not gotten much attention, the approach of
strained silicon on insulator (SOI) appears to be gaining
A new technique involves creating a buried SiGe layer in the nFET
device to induce tensile stress in the channel. IBM is using this
approach, called a reverse-embedded SiGe approach, because embedded
SiGe is typically used in the S/D regions of the pFET to induce
compressive stress in the channel.3 The image in Figure 3
corresponds to a structure post silicon regrowth in the S/D areas.
In this work, IBM Systems and Technology Group (Hopewell Junction,
N.Y.) used a SiGe stressor (SiGe/silicon bilayer) to impart uniaxial
tensile strain (400 MPa) in the channel, which led to 40% mobility
enhancement and 15% drive current improvement relative to a control
device with no strain. The strain in the channel is achieved through
relaxation/strain of the SiGe/silicon bilayer, and can be an
additive to the channel strain induced by other process techniques.
The IBM researchers found that a thinner SiGe layer was advantageous
for reducing strained epi defect nucleation.
Figure 3. A buried SiGe island is very
effective at inducing uniaxial tensile strain in the nFET
channel for a 15% improvement in drive current. The TEM
shows the device following silicon regrowth in the
source/drain. (Source: IBM)
Of course, once the drive current is achieved by strained silicon
and other means, it is up to the low-resistivity junctions to carry
this performance out through the interconnects. Junction engineering
and optimization of silicides, even new materials, become critical
as more strain techniques are employed.
There are essentially three approaches to metal gate
implementation: metal-inserted poly stack, fully silicided gate (FUSI)
and dual-metal gate by replacement gate (Table 2). Companies are
likely to take different approaches based on their product line mix
(high performance vs. low power and low standby power),
manufacturing expertise and roadmap for implementation. Low
operating power and low standby power are strongly driven by cost,
while it is possible that high-performance devices could use more
exotic metal solutions.
At an Applied Materials' event at the International Electronics
Device Manufacuturers Conference (IEDM) in December, Farhad Moghadam,
senior vice president of Applied Materials (Santa Clara, Calif.),
referring to the dual-metal gate option, stated: "The nFET metal
gate has been proven from a materials standpoint, but there is no
convergence on the pFET metal."
Though there have been many papers published, very few companies
have gone public with their plans regarding high-k/metal gate
introduction into manufacturing. "At 32 nm, we have a clear intent
to get there. We are currently moving into mainstream development,"
said Suresh Venkatesan, director of Austin Silicon Technology
Solutions at Freescale Semiconductor. Venkatesan admits that while
identifying the best pFET metal has been a problem, there is not an
inherent problem with the pFET itself. He says that through the use
of a buried SiGe channel, strained SOI substrate and other strain
techniques, good pFET performance and reliability can be attained
without a metal gate.
FUSI approaches have reached the implementation stage for some
companies. According to Serge Biesemans, director, CMOS Device
Technology Group, IMEC (Leuven, Belgium), the keys to successfully
implementing FUSI lie in understanding and optimizing the
silicidation processes. At IEDM, IMEC demonstrated the
manufacturability of dual FUSI gates, meeting the International
Technology Roadmap for Semiconductors (ITRS) requirements for low
power at 45 nm.4
One dual-metal gate option presented by Sony (Kanagawa, Japan) at
IEDM5 used a damascene W/TiN/HfO2 gate stack
for the nFET device and a W/TiN/HfSix/HfO2
stack for the pFET to attain drive currents of 1050 and 710 µA/µm at
1 V Vdd. Further integration of the pFET on (110)
orientation substrate enabled even higher drive current.
Samsung (Kyunggi-Do, Korea) engineers presented an approach to
metal-inserted poly stack at IEDM.6 In this process,
after gate dielectric deposition, TaN electrode was deposited by
advanced vapor deposition on HfSiON or HfO2, followed by
poly deposition. Drive currents of 620 and 230 µA/µm were attained
for the nFET and pFET, respectively, with no added strain
techniques. The study determined that low and symmetrical threshold
voltages (Vt) could be attained without counter-channel
doping, which complicates many dual-metal gate approaches. Part of
the advantage of this process is the simplicity (no replacement gate
and the use of existing materials). However, the new deposition
technology had to be applied to attain the TaN with proper
characteristics, and TaN thickness is critical because it has a
strong effect on electrical parameters, including gate leakage, Vt
and mobility characteristics.
On the fence with finFETs
As gate length approaches ~30 nm, the gate loses control of the
charge in the channel. Two solutions appear at hand: ultrathin-body
SOI and multi-gate FETs. Though several industry experts are opposed
to multi-gate approaches, working circuits have been demonstrated at
the 65 nm node.
"One of the questions we have is 'Is the finFET more variable
than a planar device?' Once we determine the answer to that
question, we can take the next step in evaluating this
architecture," Venkatesan said. Ghavam Shahidi, IBM fellow, has been
outspoken on the topic of finFETs, stating that if 3-D transistors
were going to be used, they would have been used by now and,
reiterating his stance at the Applied Materials' event at this
year's IEDM, said that finFETs will not be used at the 32 nm node.
What seems clear is that 3-D structures may not be applied
throughout the industry at once. But there is strong motivation for
going to finFET-type structures for certain applications, especially
for analog/mixed-signal devices, where gain and linearity are
critical performance metrics.
Multi-gate devices like finFETs have superior electrostatic
integrity and control over short-channel effects. Essentially, by
containing or fully surrounding the channel with the gate, the
electric field is nearly uniform throughout the channel. As a
result, the transistor behaves like a fully depleted device. Some of
the advantages to the design are the complete lack of well implants,
no latch-up, and reduced parasitic capacitance and resistance
problems associated with shrinking space between transistors.
Infineon Technologies (Munich, Germany) recently demonstrated
finFET circuit-level results (a 3000-transistor chip) with
multi-gate finFET transistors fabricated in 65 nm SOI.7
Using a combination of metal gate and SiON dielectric, the fin was
completely undoped. Most impressive was that there was nearly an
order of magnitude (90%) reduction in leakage current with finFETs
relative to the planar devices. This test demonstrated that
potential roadblocks in finFETs - fin height, width control and
process complexity - are surmountable. For Infineon, finFETs will
have the potential to be useful for wireless RF devices at up to ~10
MHz. An Infineon spokesman has said that multi-gate devices will
probably be necessary at 32 nm, and perhaps 45 nm.7
Another company that is actively pursing 3-D structures is Intel
(Santa Clara, Calif.). At IEDM, they demonstrated a floating body
cell (FBC) with independently controlled double gates that are
self-aligned to the S/D for high-density embedded memory.8
The design is attractive because it features a small cell size and
no storage capacitor (since charge is stored in the SOI body). This
FBC is potentially easier to integrate than embedded DRAM.9
Intel noted that very aggressive scaling of body thickness, gate
length and back-gate oxide thickness are required to simultaneously
achieve high-speed, low-voltage and good-retention characteristics,
although the design eases the scaling restraints of other FBC
Intel fellow Tahir Ghani stated that existing strain techniques,
in principle, should be able to be applied to finFET transistors. He
noted, however, that they may be applied in different ways than they
have been for planar devices.
The good news on the chip interconnect side is that there will be
few process and architectural changes at the 32 nm node. The biggest
changes occur with respect to the low-k dielectric in logic devices
and the transition to copper interconnects for memories.
At the 45 nm node, leading device makers implemented the first
porous low-k chemical vapor deposition (CVD) films (k~2.6) at the
critical levels, which represented an enormous integration and
engineering challenge for the fabs.10 For example, the
low-power platform presented by STMicroelectronics (Geneva,
Switzerland) and Freescale Semiconductor (Austin, Texas) uses
ultralow-k (k~2.5) at M1-M7 levels, with TEOS at M8 and M9. In
contrast, IBM's 45 nm interconnect stack uses a porous low-k
selectively only at the switching-delay (RC)-dominated 2X levels
(M4-M6), with low-k (k=3.0) at the 1X and 4X levels (M1-M3 and
M7-M8) and fluorinated TEOS at the M9 and M10 levels. Likely
extensions of these 45 nm stacks to 32 nm will involve enhancement
of the barrier technology (making barriers thinner, yet just as
reliable) and eliminating any assist layers, such as chemical
mechanical planarization (CMP) caps and gradual improvements in the
low-k. "As we move to 32, there are chances to optimize UV cure and
provide more efficient removal of the porogen in the film," said Tim
Archer, senior vice president of the dielectrics group at Novellus
Systems (San Jose).
Incorporating copper interconnects into memory devices features
slightly different challenges than those for logic. As detailed by
Gurtej Sandhu, manager of strategic process R&D at Micron Technology
(Boise, Idaho), at a recent Semiconductor International
webcast, "Advanced Material Solutions for Interconnects," flash
memory devices, because of their higher electric fields, require
thicker barriers and denser oxides while meeting the fill
requirements of tight-pitched M1 (Figure 4). Contact to M1 is made
using very high-aspect-ratio vias (~10:1).
Figure 4. The interconnect of a flash
device shows on-pitch Metal 1 with high-aspect-ratio vias
above, which press the capabilities of barrier/seed coverage
and copper fill. (Source: Micron)
In terms of barrier and seed technology, barrier continuity is an
ongoing issue in high-aspect-ratio features. Some memory
manufacturers are looking at simple alloys of copper involving
aluminum or magnesium (which migrate and become the barrier on
anneal). Ruthenium-based oxides involve a more complex approach, but
are still being investigated. Metal cap layers (electroless CoWP/CVD
tungsten) face process margin and integration challenges. From a CMP
standpoint, improvements are needed to polish tungsten caps and
remove residual ruthenium seed.
One of the significant changes in multi-level interconnects that
may be implemented at the 32 nm node is the replacement of tungsten
contacts with copper. Today, companies typically use titanium for
improved contact, a sputtered TiN barrier followed by a tungsten
nucleation layer and tungsten fill (CVD films). Copper plugs, with
their lower contact resistance, alleviate the rapid rise in
resistance as tungsten contacts scale below ~70 nm in diameter.
Contact resistance impacts both RC and power consumption. As
contacts scale, copper electroplating also provides an answer to the
keyhole defects associated with tungsten deposition.
Of course, copper contacts must be properly contained within a
barrier film, and not allowed to diffuse into the silicon and poison
the transistors. According to engineers at IMEC, achieving adequate
yield and reliability with a copper contact process requires an
optimized barrier.11 In this work, poor barrier quality
was related to the formation of a copper silicide found in the S/D
regions and around the gate. Poor barrier quality gave rise to yield
loss in junctions and gate dielectrics and reduced
A thin barrier is desired for lower contact resistance, while a
thicker barrier ensures higher reliability. Therefore, a trade-off
is required in manufacturing. Barrier resputtering, performed to
thin the barrier at the bottom of the contact and improve sidewall
coverage, can have an adverse effect on reliability.
In a keynote address at IEDM, Chang-Gyu Hwang, president and CEO
of Samsung Electronics' semiconductor business, said that 3-D
integration will drive the next stage of unprecedented growth in the
semiconductor industry.12 "Unlike the paradigm shift from
the personal computer to mobile and digital consumer applications,
the introduction of massive-scale fusion technology - which
represents the organic convergence of information technology,
biotechnology and nanotechnology - will bring together a wide range
of technology-related professions as the foundation for a new
technology frontier," Hwang said. "Fusion will be enabled by 3-D
technology integration. The core element needed to usher in the new
age will be a complex integration of different types of devices,
such as memory, logic, sensor, processor and software, together with
new materials and advanced die-stacking technologies, all based on
3-D silicon technology."
IMEC recently demonstrated 3-D stacked ICs by stacking extremely
thin bulk silicon wafers, connected by direct copper-to-copper
thermo-compression bonding. Functional through-silicon 3-D via
chains were realized (Figure 5), with densities up to 10,000/mm2
and a via pitch of only 10 µm, via height of 20 µm and 5 µm
SEM of a 3-D via chain with 10,000 vias/mm2
density after etching the silicon in the top die. (Source:
In this process, the copper vias are processed using copper
damascene just after the contact layer and before the
back-end-of-line (BEOL) interconnect stack. Vias are opened at the
wafer backside by aggressively thinning the wafer down to 10-20 µm
by grinding, CMP and etch. The wafer is diced by standard processes,
and the dice are attached and electrically interconnected to a
copper/dielectric landing substrate using thermo-compression
bonding. This demonstration is important because of the density and
interconnect sizes achieved by the potential extension to
|1. A. Hand, "Double
Patterning Takes Hold as Bridge Technology,"
Semiconductor International, November 2006, Vol. 29, No.
12, p. 34.
|2. L. Peters, "Options
Narrow at 45 nm," Semiconductor International,
January 2006, Vol. 29, No. 1, p. 36.
|3. R. Donaton, "Design
and Fabrication of MOSFETs With a Reverse Embedded SiGe
Structure," IEDM 2006, p. 465.
|4. T. Hoffmann,
"Ni-based FUSI Gates: CMOS Integration for 45 nm Node and
Beyond," IEDM 2006, p. 269.
|5. Y. Tateshita,
"High-Performance and Low-Power CMOS Device Technologies
Featuring Metal/High-k Gate Stacks with Uniaxial Strained
Silicon Channels on (100) and (110) Substrates," IEDM 2006,
|6. S.K. Han, "Highly
Manufacturable Single Metal Gate Process Using Ultra-Thin
Metal Inserted Poly-Si Stack (UT-MIPS)," IEDM 2006, p. 621.
|7. R. Wilson, "Infineon
Shows Full Chip Employing finFET," EDN, Dec. 4, 2006.
|8. "I. Ban et al.,
"Floating Body Cell with Independently-Controlled Double
Gates for High Density Memory," IEDM 2006, p. 573.
|9. A. Steffora
Mutschler, "Intel Eases High Density Memory Scaling with
Floating Body Cell," Electronic News, Dec. 15, 2006.
|10. L. Peters, "Making
Low-k Dielectrics Work," Semiconductor International,
June 2006, Vol. 29, No. 6, p. 63.
|11. G. Van den Bosch
et al., "Impact of Copper Contacts on CMOS Front-End Yield
and Reliability," IEDM 2006, p. 93.
|12. Samsung, "Samsung
Says 3-D Silicon Will Drive Boundless Industry Growth in
Fusion Era", press release, Dec. 12, 2006.
|13. B. Swinnen, "3-D
Integration by Cu-Cu Thermo-compression Bonding of Extremely
Thinned Bulk-Si Die Containing 10 µm Pitch Through-Si Vias,"
IEDM 2006, p. 371.