/ EETimes (11/26/2007 12:11 PM EST)
SAN JOSE, Calif. At its developer conference in Japan this week, Rambus Inc. is expected to demonstrate technologies that could enable links to memory chips delivering at up to a terabyte/second. The company believes its signaling techniques will provide a lower cost alternative to 3D chip stacking.
Delays between microprocessors and external DRAMs have long been a bottleneck in system performance. "Today the memory bandwidth requirements are going up dramatically due to multicore processors running multiple threads per core," said Kevin Donnelly, a senior vice president of engineering at Rambus.
Attacking this problem, Rambus will demonstrate multiple memory channels running at up to 16 Gbits/s each, about four times faster than individual channels currently in development. The Tokyo demonstration is expected to show a 65nm controller linked to two 65nm RAM devices with aggregate throughput of up to 32 Gbytes/s to each memory chip.
Rambus will achieve that throughout by applying three signaling techniques to relatively traditional discrete devices. The controller is in a flip-chip package and the RAMs use wire bonding.
"Our intention is to show something that is realistically manufacturable a few years out," said Steve Woo, a technical director at Rambus. "It would not be unreasonable to see this need [for a Tbyte/s memory chip] in 2010 or 2011," he added.
"People are looking at through-hole vias and chip stacking to solve these problems, but these approaches have thermal issues and other problems," said Donnelly. "If you can achieve these signaling rates with discrete components, rather than a relatively exotic technology, there are definite cost advantages," he added.
In March, IBM Corp. announced it is making a power amplifier that uses as many as 100 through-hole vias to link to a power ground plane. The company touted the move as a first step toward the 3D stacking technology it will also apply to linking Power processors and cache SRAMs for its BlueGene/L supercomputers, opening up significantly faster links between the CPUs and their memory.
More than a dozen companies and research groups are pursuing through-silicon vias and related techniques including Elpida, IMEC, Samsung and Sematech as well as startups Cubic Wafer, Tezzaron, Ziptronix and ZyCube. However, analysts said the approach is still immature and faces multiple hurdles including how to cools the stacks.
In an interview with EE Times, Bernie Meyerson, chief technologist of IBM's systems and technology, defended the technique's potential to be both manufacturable and to open up new approaches in systems design.
"There is no reason it would not be [economically viable]," Meyerson said. "IBM has a long history in deep trench structures and through hole is not that different from deep trench. In addition, our wafer thinning capabilities are also getting very good," he said.
"If we can do this for cache, you have to ask what other applications could you enable if you affectively had infinite cache," Meyerson said. "There are many issues about latency and delay when devices are far away, and there also is the issue of bandwidth per watt," he added.
Meyerson would not comment on IBM's plans to commercialize the through-hole technology.
In its demo, Rambus is expected to use a 16x multiplier of the chip's internal 500 MHz clock, sending a total of 32 bits each clock cycle. That's four times the eight bits per 400 MHz clock used on the company's current XDR memory interface.
In addition, Rambus will use the same 32x clock rate and differential signaling on the command as well as the data lines between the devices. Traditionally the command lines use relatively slow, wide buses.
The shift to point-to-point command lines means each chip will have to have its own independent command links. In addition, engineers will not be able to route data across various chips on a bus.
Neither factor should create problems, Donnelly said. The high-end systems Rambus is targeting typically have only a few large memory chips. In addition, switching to more narrow and fast links should mean power consumption will be about the same or even lower than when using the wide, slow bus.
Rambus is making no comment on any plans for products using the technology in the Tokyo demonstration.
"We are not recruiting partners at this time. My job is to develop new technology, and we are an early stage of evaluating new silicon for this approach," Donnelly added.