San Jose, Calif. -- The lithography world has suddenly turned
upside-down as the industry gets socked by a double whammy: The window
of opportunity is slowly closing on extreme-ultraviolet (EUV)
lithography for IC production, but the most likely alternative--a
version of 193-nanometer immersion--is proving expensive. The added
costs could have some serious implications for
At last week's SPIE Advanced Lithography conference here, there were
troubling signs that oft-delayed EUV technology could get pushed out
even further, to the 16-nm node, in 2013--if it materializes at all.
That could set back leading-edge chip makers such as Intel and Samsung,
which were hoping to get their hands on working EUV tools for the
early-development phases of the 22-nm node in 2011.
EUV's problems open the door for a crop of emerging technologies,
such as immersion, maskless and nanoimprint lithography. But at least
for the 32- and 22-nm nodes, the leading contender is 193-nm immersion,
equipped with the new buzzwords "double exposure" and "double
Although various entities have proven the viability of double
exposure and double patterning, the technology is more expensive than
today's patterning schemes. That means chip-manufacturing costs could
take a big hit over time. There are other ominous implications for the
continued push to reduce IC
bit prices at each process technology node.
"With double exposure, bit costs will continue to decelerate, but not
at the rate we've experienced in terms of historical trends," said Harry
Levinson, manager of strategic lithography technology for the Technology
Research Group at Advanced Micro Devices Inc.
At SPIE, Applied Materials, Hynix, IBM and IMEC separately presented
methodologies that promise to reduce the costs of the technology.
Regarding the delay of EUV for the early stages of the 22-nm node,
AMD's Levinson summarized the situation: "I'm a little disappointed.
Time is running out [for the technology]."
Indeed, "If we don't find [new lithography] solutions, Moore's Law
breaks down," said analyst G. Dan Hutcheson, chief executive at VLSI
Hutcheson still believes there's a place for EUV. "I would say that
EUV has a future. It's going to be sometime after 22 nm. EUV will
pop up at 16 nm," he said. Hutcheson was more pessimistic about
maskless and nanoimprint lithography. "Maskless is not [likely] to make
it other than for research," he said. "Nanoimprint has applications
other than semiconductors."
That leaves 193-nm immersion as the near-term choice. "A year ago,
people were saying double patterning is not going to happen. Now
everyone is talking about double patterning," said Hutcheson.
The pessimism surrounding EUV deepened recently when IBM Corp.
delivered a bombshell by saying that EUV was not expected to be ready
for the early development phases at the 22-nm node (36.5-nm half-pitch)
for logic, as the company previously hoped. Instead, IBM and its
development partners--including AMD, Chartered, Freescale, Infineon,
Samsung and others--claim they will extend 193-nm immersion lithography
down to the 22-nm node, thanks in part to double-patterning or
"EUV will be late for early development at the 22-nm node," George
Gomba, IBM distinguished engineer and director of lithography technology
development, said during a presentation at SPIE. "Water immersion will
be the only solution that meets the two-year cycle and requirements at
EUV's main champion, Intel Corp., agreed with IBM's assessment. "We
would say the same thing," said Intel senior fellow Yan Borodovsky,
director of advanced lithography in the company's Technology and
Manufacturing Group. EUV still suffers from the "same issues" that have
dogged development all along, he said, including the well-documented
lack of photomasks, power sources and resists--and a staggering price
tag of possibly $70 million per lithography machine.
"The devil is in the mask, the source and the cost," Burn Lin, senior
director of the micropatterning division at silicon foundry giant Taiwan
Semiconductor Manufacturing Co. Ltd., said at SPIE.
EUV is dead in the water, said Gerhard Gross, CEO of maskless-lithography
IMS Nanofabrication AG. "It's not coming," he said. "I don't think
anybody is committed to developing the mask infrastructure."
Intel's Borodovsky said the next 12 to 18 months will be critical for
the realization of EUV, but he insisted the technology is still on
Intel's road map for use at the 22-nm node in 2011.
In fact, EUV has already been delayed several times within Intel. For
years, Intel publicly stated that it would like to deploy EUV for chip
production at the 32-nm node. But last year Intel pushed out its efforts
to bring EUV into production at 32 nm.
Using a 13.5-nm wavelength, EUV is a major departure from today's
conventional lithographic tools. The
processing steps take place in a multimirror vacuum chamber. The
optical elements are basically defect-free mirrors, which reflect light
by means of interlayer interference.
Progress in bringing EUV to market has been slow. For example, to
achieve a throughput of 100 wafers an hour, an EUV tool must have a
source that generates 100 watts of sustained power. So far, the best
source can generate only one-quarter of that amount in burst mode.
Recently, equipment giant ASML Holding NV shipped EUV "demo" tools to
both the IMEC chip-making research consortium in Leuven, Belgium, and
Albany Nanotech, the New York-based research institute. ASML is
developing a more advanced "preproduction" EUV machine, which is slated
to roll out in the second half of 2009. Last week, ASML claimed a
breakthrough in the arena, as it used the tool to pattern 32-nm dense
lines and contact holes.
"It's difficult technology," said Peter Jenkins, vice president of
marketing for ASML. "We believe the ability to show a sub-30-nm image is
Not to be outdone, rival Nikon last week outlined its EUV road map,
claiming it will ship two prototypes by year's end. They will be
followed by a production machine by the end of 2009, said Kazuaki
Suzuki, a manager for Nikon.
Behind the scenes, ASML, Canon and Nikon are also racing one another
to develop new 193-nm immersion scanners equipped for the
double-patterning, double-exposure era. The first such machines are due
out by mid-2008 or so.
A few chip makers, reportedly including Micron Technology Inc., have
already deployed double-patterning techniques in IC production. Double
patterning requires that the exposures be done twice, first exposing
half the lines, etching and performing the other steps. Then, another
coating of resist is spun onto the wafer and the other half of the
pattern is exposed in the interstitials, or between the first set of
lines. The approach is expensive and slow, but technically relatively
easy, although it requires overlay accuracy of about 2 nm.
Double exposure, for its part, involves exposing one set of lines and
then, before other process steps are done, moving the exposure to an
adjacent space and exposing the second set of lines. While double
exposure is faster than double patterning, the trick is to find a
nonlinear resist--that is, a resist chemistry that can absorb weak light
from the adjacent exposure without creating a pattern.
For logic production, IBM last week proposed a double-exposure
technique based on dark-field, double-dipole illumination for
back-end-of-line processes. Double-dipole illumination divides the mask
pattern into two layers--and X and Y axes--and then exposes them twice.
The technology enables two exposures in the same resist, thereby driving
down overall costs, said Martin Burkhardt, research staff member in
IBM's advanced-patterning unit, during a presentation here.
In the lab, IBM used a 193-nm immersion
scanner with a numerical aperture (NA) of 0.93. Using the Maskweaver
optical proximity correction tools from ASML and a proprietary trilayer
resist, IBM says it has demonstrated devices with metal-one pitches at
90 to 100 nm.
For its part, IMEC has developed a double-patterning technique that
enables 50-nm half-pitch, single-damascene designs. IMEC used a 193-nm
immersion scanner with an NA of 0.85. Using a rival quasar illumination
scheme, IMEC also deployed a 6 percent soft-phase-shift mask and an
organic bilayer resist. Also required are "lithography-friendly
designs," said Maaike Op de Beeck, a researcher at IMEC.
DRAM production, Hynix Semiconductor Inc. is using "spacer
formations" in double patterning, enabling 32-nm designs with a 193-nm
immersion scanner. According to Hynix, the spacer process involves the
following steps: top hard-mask etch, nitride spacer, oxide deposition,
CMP and nitride strip.
Applied Materials Inc. drew intense interest at SPIE by demonstrating
a similar method--a self-aligned double- patterning technology aimed at
dry rather than immersion lithography. The scheme is deployed by using
Applied's Advanced Patterning Film and plasma-enhanced chemical vapor
deposition system. It enables 32-nm lines and spaces on a 193-nm "dry"
scanner, said Farhad Moghadam, senior vice president and general manager
of Applied Materials' Thin Films Group.