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SOI

Why SOI?

SOI Challenges

SOI Wafer

Is SOI worth the effort?

Why SOI?

Silicon-on-insulator has been around in one form or another over the past 40 years. In the past, SOI was mainly used for special applications or in niche markets that require high radiation hardness, high breakdown voltages, high temperature compatibility or low coupling to substrate.

In recent years, however, we are seeing a resurgence of interest in SOI and SOI is now making inroads into mainstream CMOS technology. This is in part triggered by a decision by IBM in latter part of 1990’s to adopt SOI CMOS technology as the process technology for its high performance microprocessors.
Microprocessors built on SOI technology by IBM have been commercially available since 1998. Other companies, such as Motorola, AMD and NEC have also jumped into SOI bandwagon to develop SOI CMOS technology for their high performance logic products or low power applications at 0.18um or 0.13um technology node. AMD is currently shipping its entire microprocessor lines built on SOI CMOS process at 130nm node and will soon introduce 90nm SOI CMOS microprocessors. Intel is still committed to the bulk CMOS technology at 90nm node for its microprocessors but actively investigating SOI as an option for future generations.

This newly heightened interest in SOI technology is fueled by several factors.

First, bulk CMOS transistors are approaching its scaling limit, making chip manufacturers scramble to find other alternatives.

Second, SOI transistors provide superior speed performance, density and other advantages, such as latch-up free operation, over bulk CMOS transistors. Speed advantage of SOI is mainly due to reduced junction capacitances and body effect. For leading edge high performance logic products such as microprocessors, SOI CMOS is an attractive alternative to bulk CMOS.

At a given technology node, SOI CMOS transistors are said to be about 25% faster than bulk transistors. This is equivalent to a speed difference of one technology generation. Therefore, theoretically speaking, and if 25% speed difference is valid, SOI technology puts products built on SOI process one generation ahead of competition delivering the same products on bulk CMOS process.

Third, SOI is better suited for low power and low voltage applications than bulk because of low parasitic junction capacitance and superior transistor on-off characteristics. As hand-held and portable devices operating on battery power become more pervasive, SOI technology becomes more attractive to address these markets.

Fourth, knowledge and experience accumulated from the past on SOI material, process technology and device design now makes production of SOI chips economically feasible and competitive with bulk CMOS process.

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SOI Challenges

Although SOI CMOS provides a number of advantages over bulk CMOS, there are technical challenges in SOI and conversion from bulk CMOS to SOI CMOS technology is not pain-free. Device, process, material and yield issues must be re-examined carefully to maximize the benefit and to reduce the cost of SOI.
SOI transistors typically operate with its body (substrate) floating, either in a partially depleted mode or a fully depleted mode. This floating body in SOI transistors creates unique SOI issues such as kink in the drain current, hysteresis effect, and charge dump in the pass gate transistors. Self-heating in SOI transistors because of poor thermal conductivity of buried oxide also needs to be understood and properly dealt with. Porting the circuits designed for bulk CMOS technology to SOI technology is therefore not straightforward and takes a great deal of optimization effort.

Some key challenges in SOI process technology are the following: SOI wafer defectivity, stress on thin SOI film, metrology involving multiple film stack.

SOI wafers with manufacturing quality are now available in volume quantity from commercial SOI wafer manufacturers. SOI wafers are more expensive than bulk. However, today’s advanced CMOS process is complex and expensive anyway, so the wafer cost difference in SOI and bulk technology is not as critical as in the past. On the other hand, manufacturing issues such as defects in SOI starting material and generated during processing, metrology, and yield learning have yet to mature to a level to match bulk technology.

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SOI Wafer

The lack of high quality SOI wafers in volume quantity was one of the factors dragging the use of SOI process in the past in the mainstream technology. However, in recent years, there has been a great deal of progress in solving technical and economical issues by commercial SOI wafer vendors such as Ibis, Kopin, SOITEC, and Silicon Genesis.

Two main SOI wafer manufacturing process have emerged as a commercially viable SOI wafer production process; SIMOX and wafer bonding.

In SIMOX process (Separation by Implantation of Oxygen), high dose oxygen is implanted into the substrate silicon to a desired depth. The oxygen implant dose is typically in the range of 1e16 to 1e17. The wafer is then subjected to a heat treatment, during which SiO2 is formed inside silicon substrate, leaving thin SOI silicon film over the buried oxide.

A bonded SOI wafer is created by bonding two wafers at the surface of oxides, which were grown at the top of each wafer. After wafer bonding is formed, most of one of the wafers is sliced off, leaving a thin SOI silicon film on top of the oxide. The other wafer serves as a holder and is called the handle wafer.

In a bonded SOI wafer process called SmartCut used by SOITEC, the surface of each wafer is first oxidized to a desired thickness, and the two wafers are brought into contact at the oxide surface. One wafer is implanted with heavy dose hydrogen so that the implanted wafer can be later broken off at the implant depth. When the two wafers in contact are subjected to a heat treatment, a strong bond is formed at the oxide interface between the two wafers. Slicing off most of one the wafers leaves thin SOI silicon film over the oxide at the wafer surface. Sliced-off wafers can be recycled for repeated use.

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Is SOI worth the effort?

In an invited paper delivered at IEDM 2003 (D. Greenlaw, et. al., pp. 277-280), AMD described methodologies and results on manufacturing improvement to bring its SOI technology to high volume manufacturing at 130nm and 90nm node. This is the culmination of 5 years of SOI effort at AMD. In this presentation, AMD demonstrates SOI challenges can be overcome and it is possible to bring SOI yield and performance to match or exceed bulk CMOS technology. The evidence is in the full volume production of AMD Athlon and Opteron microprocessor lines at 130nm node, and at 90nm node in the near future.

Achievement by AMD is particularly encouraging for the semiconductor industry and SOI community because AMD is the first company to bring high volume SOI products to a mass merchant market in consumer applications. However, one also needs to ask a question if SOI is worth the effort. Intel, for example, is still committed to bulk CMOS technology at 90nm node for its microprocessors, and its bulk CMOS is as good as any other 90nm technology, whether SOI or bulk.
Whether SOI CMOS provides 25% performance advantage over bulk CMOS is a subject of debate. Although SOI definitely has its own benefits, it is difficult to precisely determine SOI benefit over bulk because apple-to-apple comparison between the two is not easy. Therefore the answer to that question if SOI is worth the effort is probably a matter of belief and commitment. If you believe the benefit of SOI and its competitive edge over bulk counterpart -based on some kind of your own metric, of course- then you have an answer. AMD seems to have found that answer early.

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Monthly Forum
April 2005

Flash Memory Technology:

Promises and Challenges

May 2005  

Managing Stress in the sub-100nm Era

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