MOSFET: Toward the Scaling
A Brief History of MOSFET
MOSFET at the 130nm and 90nm Technology Nodes
Recent Trends in MOSFET Innovation
Toward the Scaling Limit
MOS transistor is the building block of integrated circuits, and
is the engine that powers them. Today’s most complex ICs,
such as microprocessors, graphics, and DSP chips, pack more than
100 million MOS transistors on a single chip. Integration of one
billion transistors into a single chip will become a reality before
2010. This ultra-high level of transistor integration is the result
of relentless transistor scaling for the past 40 years.
The most advanced CMOS
technology currently in volume production is the 130nm technology.
At the 130nm node, the gate length of the high-performance MOSFET
is around 60nm. For the upcoming 90nm technology, the gate length
will be around 45nm. Beyond that, only a few more transistor scaling
may be feasible for the conventional MOSFET as we know it today.
Further scaling may require
a different MOSFET architecture, such as non-planar MOSFET built
on SOI. However, the current planar MOSFET structure may show resilience
with breakthroughs in such critical areas as high-k dielectric and
gate electrode engineering, enabling scaling of the conventional
MOSFET below a 20nm gate length.
Brief History of MOSFET
For a brief history of
For a basic understanding
of how transistors function, visit
The operating principle
of the MOSFET transistor was first described in Lilienfield’s
historical patent issued in 1926. It took another 34 years before
Kahng and Atalla successfully built a working MOSFET in 1960.
For the past 40 years,
the semiconductor industry and academia have relentlessly pushed
transistor scaling. Along with scaling, the MOSFET transistor evolved
from the P-ch MOSFET in the 1960’s to the N-ch MOSFET in the
1970’s. A good understanding of gate oxide quality, such as
interface traps, fixed and mobile charges, and a good control of
gate oxide quality in a manufacturing environment enabled industry
to make the transition from PMOS technology to a higher-performing
NMOS technology in 1970’s.
Another important development
in the evolution of the MOSFET is the replacement of metal gate
with poly-silicon gate. Early MOSFET used aluminum as a gate electrode,
hence the name MOSFET. While a metal gate is ideal from a purely
transistor-architecture standpoint, it puts a great deal of constraints
on process integration. For example, the thermal budget and self-alignment
capability of source/drain to the gate had to be compromised with
the metal gate. Use of heavily doped poly-silicon as a gate material
opened a whole new vista and allowed tremendous improvement in scalability
of MOS transistors and technology.
The idea and ability to
integrate both P-ch and N-ch MOSFET on a single chip led to the
birth of CMOS technology in the mid 1970’s. Since the 1980’s,
CMOS technology has become a de facto mainstream IC manufacturing
technology. N-ch and P-ch MOS transistors, when connected in CMOS
configuration, draw very little DC current during steady state.
This low-power characteristic of CMOS makes it possible to integrate
over a hundred million transistors on a single chip, as we see in
today’s advanced IC chips.
CMOS technology itself
has gone through a few important technological innovations. Initially
developed as a single-well process, with one of the two MOSFET types
built in a well, and the other on silicon substrate, it evolved
into a twin-well process where each type of MOSFET sits on its own
optimized well. After that, triple-well CMOS technology was developed
for certain applications.
Another breakthrough in
CMOS technology came with the development of dual-gate CMOS technology.
Early on, n+ doped poly-silicon was used as a gate material for
both N-ch and P-ch MOSFET. This made P-ch MOSFET operate in the
buried-channel mode, while N-ch MOSFET operated in the surface-channel
mode. Suppression of short-channel effects such as punch-through
is more difficult in buried-channel transistors, leading to a scalability
problem in P-ch MOSFET. With the use of implanted poly in a self-aligned
CMOS process, dual-gate CMOS was realized that had n+ doped poly-Si
gate for N-ch MOSFET, and p+ doped poly-Si gate for P-ch MOSFET.
This enabled both N-ch and P-ch MOSFET to operate in surface-channel
In today’s advanced
CMOS technology, dual-gate CMOS is the standard feature, along with
twin-well or triple-well architecture.
Up until now, MOSFET scaling
has proceeded based on the scaling theory without serious roadblocks.
MOS transistors with a gate length as short as 10nm, although experimental,
have been demonstrated.
The scaling theory, based
on a constant E-field, requires supply voltage, threshold voltage,
gate length, and gate oxide thickness to be scaled down by a scaling
factor. The doping level in the channel must be scaled up by the
same scale factor. The junction depth of source and drain also needs
to be scaled down to suppress the short-channel effect.
Another important aspect
of transistor scaling is the scaling of parasitic resistances and
capacitances. These parasitic components do not necessarily scale
with transistor scaling. Therefore, it becomes increasingly critical
to minimize parasitic components in order to get the best return-on-scaling
on transistor performance. A good example to address this issue
is the silicidation of drain, source, and gate. Cobalt silicide
used in advanced CMOS technology dramatically reduces parasitic
resistances in the device.
Transistor scaling, in
practice, has not followed exactly the constant E-field scenario.
For performance reasons and due to product requirements, scaling
of supply voltage did not happen as fast as geometrical scaling,
such as gate length and gate oxide thickness. Because of this, the
electric field in the device increased with scaling, resulting in
aggravation of short-channel effect (SCE). In addition, it also
increased reliability concerns such as hot carrier effect (HCE)
and gate oxide reliability. Various transistor design techniques
have been proposed and investigated to deal with SCE and HCE.
One of the most important
developments in transistor design to deal with SCE and HCE is the
use of lightly doped drain (LDD) in conjunction with poly-Si gate
sidewall spacer. This technique, introduced in the industry at late
1970’s, has become a standard feature for sub-micron transistors,
typically having gate lengths of 0.50um and below. Various other
ideas have been proposed and adopted in transistor design. These
include retrograde channel doping, super-steep retrograde channel,
halo or pocket implant with a large tilt angle, pre-amorphization
implant (PAI), notched gate, L-shaped spacer, offset spacers, MDD
(medium doped drain) and source/drain extension.
A good overview of MOSFET
scaling and issues on transistor scaling below 50nm gate length
can be found in “CMOS Design Near the Limit of Scaling,”
by Y. Taur, pp. 213-221, March/April 2002, IBM Journal of Research
In today’s advanced CMOS technology, MOS transistors are typically
implemented in a dual gate CMOS configuration: n+ poly gate for
NMOS, and p+ poly gate for PMOS. Dual-gate CMOS allows both N-ch
and P-ch transistors to operate in a surface-channel mode. However,
it presents process integration issues such as boron penetration
in the p+ poly gate, which causes device instability and gate oxide
reliability problems in the P-ch MOSFET. Reduction of the thermal
budget to minimize boron penetration can cause insufficient dopant
activation in the gate poly, leading to poly depletion problems.
These are some of the challenges in further scaling of MOSFET below
a 100nm gate length.
at the 130nm and 90nm Technology Nodes
The most advanced MOS
transistors used in volume production today are probably those of
Intel’s used in their 130nm logic technology. For generations,
Intel has displayed its masterful skills of transistor design, placing
its transistors at the top of the competition for transistor performance.
According to an Intel
paper delivered at IEDM 2001, transistor gate length and gate oxide
thickness at the 130nm node is 60nm and 1.5nm, respectively. Transistor
drive current is 1300uA/um for N-ch and 660uA/um for P-ch at Vdd=1.4V
with off-state leakage current of 100nA/um. These are the best performance
reported in the industry at the 130nm node.
For 90nm technology, Intel
presented a paper at IEDM in 2002 for its initial version of 90nm
technology, followed by a production-ready 90nm process presented
at IEDM 2003. Intel’s production version 90nm technology is
quite different from the previous version a year ago, in terms of
integrating strained silicon into the CMOS process.
In a paper delivered at
IEDM 2002, Intel described implementation of strained-silicon channel
MOSFET in its 90nm bulk CMOS technology. Intel claims a transistor
performance gain of 10%-20% for both N-ch and P-ch MOSFET by using
strained-silicon channel epitaxially grown on relaxed SiGe layer.
With transistor gate length and gate oxide thickness of 50nm and
1.2nm, transistor drive current of 1260uA/um for N-ch and 630uA/um
for P-ch is achieved at Vdd=1.2V with off-state leakage current
of 40nA/um. Judging by the published data, Intel’s MOSFET
DC performance is indeed the best in the industry at the 90nm node.
Intel’s 2002 result
seems quite remarkable in the sense that it demonstrated for the
first time integration of strained-silicon MOSFET into CMOS technology
with performance enhancement for both N-ch and P-ch. However, Intel
did not disclose the ring oscillator speed of its 90nm technology,
suggesting that the N-ch and P-ch transistor drive currents reported
in IEDM 2002 were probably obtained from two different processes,
each optimized for N-ch and P-ch separately. So, the strained-silicon
channel MOSFET with a relaxed SiGe layer did not seem ready for
full CMOS integration at Intel in 2002.
At IEDM 2003, Intel presented
a manufacturing-ready 90nm technology, in which it described a completely
different approach to implementing strained silicon in CMOS. In
effect, Intel abandoned the strained-silicon channels formed over
a relaxed SiGe layer, the method it had used in the 2002 version
90nm technology, illustrating the difficulty in integrating this
approach into the CMOS process.
In the manufacturing-ready
90nm technology, Intel took a much less aggressive approach in implementing
strained silicon. For PMOS, source and drain regions are etched,
and then embedded with compressively strained SiGe film, which exerts
a uniaxial compressive strain to the channel. The resulting P-ch
drive current with a gate length of 50nm is an astounding 700uA/um,
~10% higher than the already impressive 2002 value. This P-ch drive
current is a record high at 90nm node. The N-ch transistor does
not incorporate SiGe layer at all. Instead, tensile stress in the
channel comes from a highly tensile silicon-nitride capping layer
deposited over the silicide. The resulting N-ch drive current is
the same as the 2002 value at 1260uA/um, but Intel had to scale
down the N-ch gate length to 45nm to maintain the same drive current
as in 2002.
For more on MOSFET at
130nm and 90nm node, visit Logic section in the Technology area.
Trends in MOSFET Innovation
Up until now, MOSFET scaling
has progressed without running into a serious roadblock. Engineering
ingenuity always overcame challenges at every generation of scaling,
improving density and performance along the way. Nevertheless, complex
and performance-hungry IC products demand the highest transistor
performance at each generation, making chip manufacturers scramble
to find the best solution possible. In addition, as we approach
the physical limits of MOSFET scaling, research on other alternatives
to conventional device and process is accelerating. Some of the
topics under intense investigation are SOI, strained silicon, high-k
gate dielectric and gate stack engineering, and non-planar MOSFET.
Bulk vs. SOI
Bulk CMOS technology has been the mainstream IC manufacturing technology
since the early 1980’s. In recent years, however, several
major companies, such as IBM, Motorola, and AMD, committed to SOI
technology for their high-performance logic products. IBM, the industry
leader in SOI technology, started a serious SOI development effort
in the late 1980’s, and has been shipping products on SOI
since 1998. IBM claims a SOI performance benefit of 25%-30% at the
chip level, when compared with comparable bulk technology.
The SOI push by IBM got
a boost from the 65nm SOI technology development alliance with IBM
and AMD, announced in early 2003. AMD was the first company to use
SOI technology for products selling into the multi billion-dollar
merchant market. So its impact on the proliferation of SOI technology
could be significant. However, how quickly SOI will appeal to a
broader spectrum of IC manufacturers remains to be seen.
For more on bulk versus
SOI, go to the SOI section in the Technology area.
Because of its potential to make a dramatic improvement in
MOSFET performance, strained-silicon transistor has been a hot topic
in recent years, and is now beginning to make inroads into manufacturing
technology. Reflecting this trend, a whole session was dedicated
for the first time to strained-silicon MOSFET papers at IEDM 2003.
While the underlying physics
of strained silicon and its effect on carrier mobility is well understood,
incorporating it in a manufacturing process and delivering the promised
performance for both NMOS and PMOS in CMOS technology is not an
easy task. As mentioned previously, Intel’s original attempt
to integrate strained silicon in 2002 took a major detour in 2003,
and it settled with a much less aggressive method of implementing
strained silicon in its volume-manufacturing 90nm technology.
Many companies have been
investigating different ways to create strained-channel MOSFETs,
and reported performance gains to a different degree for NMOS or
for PMOS or for both. IBM, the leader in strained-silicon research,
for years has demonstrated performance benefit of strained silicon
in various publications and conferences. In a recent paper presented
at IEDM 2003, IBM described a process that integrates strained silicon
into fully depleted ultra-thin body SOI MOSFET without an SiGe layer
in the SOI film. Dubbed by IBM “strained silicon directly
on insulator (SSDOI),” this process involves a layer transfer
of strained silicon grown on a relaxed SiGe layer to a handle wafer
by wafer bonding after the strained silicon is capped with SiO2.
After separation of the host and handle wafers, the SiGe film is
selectively removed by polishing and etching, leaving ultra-thin
strained silicon over the buried oxide. With this technique, high
field mobility, extracted from long-channel transistors, showed
improvement of 125% for electrons and 21% for holes. These improvements
are comparable to those IBM achieved on bulk MOSFET with strained
Whether with bulk or SOI
MOSFET, the full potential of strained silicon has yet to be realized
in a fully integrated CMOS process that offers performance enhancement
for short-channel transistors.
and Gate Stack Engineering
Conventional silicon dioxide has already reached its scaling limit
because of the high leakage current for the thickness required for
today’s deep sub-100nm gate transistors. Although heavily
nitrided SiO2 improves gate leakage current, and thus extends the
SiO2 lifetime possibly down to the 65nm generation, it also has
a downside of mobility degradation. A breakthrough in gate dielectric
is necessary to enable 45nm technology. A great deal of work has
been done in the past and is currently being undertaken to develop
manufacturable high-k gate dielectrics. However, it is uncertain
at this time if high-k gate dielectric and the associated gate stack
process will be ready in time for the 45nm generation. This is a
huge task, and it poses the biggest challenge to transistor scaling
that the semiconductor industry has ever faced.
High-k dielectric material,
such as HfO2, ZrO2, and Al2O3, received attention as promising material
and results were demonstrated with these materials, HfO2 in particular.
However, there are still issues that need to be resolved before
high-k material can be integrated into manufacturing technology:
mobility degradation, interface traps, fixed charge, thermal stability,
interfacial layer property, gate leakage current, dielectric reliability,
interaction with gate electrodes, high-k film deposition and etch,
surface preparation, and thermal processing.
Gate electrode is also
an important part of gate stack engineering, whether with high-k
dielectric or with SiO2. For ultra-short channel transistors, traditional
problems associated with poly gate such as poly depletion and boron
penetration become critical issues for transistor performance and
scaling. To alleviate these problems, metal gate electrode is being
actively researched. One method, proposed by IBM, AMD, and STMicro,
uses full silicidation of gate poly using nickel or cobalt, which
can be easily integrated into a conventional CMOS process. In another
approach called replacement metal gate, the transistor is formed
using poly-Si gate, and then the poly-Si is removed and replaced
by a metal electrode. This method maintains the self-alignment capability
without having to etch the metal gate, and avoids high temperature
processing after the metal gate is formed. It is as if history repeats
itself, as we see the MOSFET gate electrode, originally made of
aluminum, go to a design of poly-silicon, and then return to metal
again, although a different metal instead of aluminum this time.
The non-planar CMOS transistor has also been actively pursued recently
as a means of easing scalability and improving MOSFET performance.
These transistors are typically built on an SOI substrate and take
various different forms and names. Some examples include FinFET,
originally developed by a group at the University of California
at Berkeley, double-gated SOI, tri-gated SOI, depleted-substrate
transistor (DST), and Omega FET –a variant of FinFET investigated
by TSMC. At present, most of the non-planar transistor work is at
the device level, and is at an experimental stage. Many process-integration
issues must be resolved before this technology can be used in a
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