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Articles:

1. Toshiba Announces 32Gb 3D-stacked Multi-level NAND Flash

2. Toshiba applies germanium to 16-nm MISFET gate stack /EETimes

3.Toshiba announces high-k/Ge gate stack technology for 16nm and beyond / DIGITIMES

 

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1. Toshiba Announces 32Gb 3D-stacked Multi-level NAND Flash

Jun 19, 2009
Jyunichi Ooshita, Nikkei Microdevices

 

Toshiba Corp developed the "P-BiCS (Pipe-shaped Bit Cost Scalable)," a 3D-stacked NAND flash memory, with 2bit/cell multi-level cell technology at the 2009 Symposium on VLSI Circuits (lecture number: 7-1).


Toshiba's 32-Gbit chip

It prototyped a 32-Gbit chip by stacking 16 levels of memory cells developed using 60nm process technology and confirmed its array operation. The chip measures 10.11 x 15.52mm, and the chip area is 6F2 (F: design rule). The effective cell area per bit is 0.00082μm2, which is smaller than that of the 32nm NAND flash memory to be rolled out by the company in 2009.

 

Multi-level operation, verification of operation at an array level

The P-BiCS is the advanced version of the "BiCS," a 3D-stacked NAND flash memory Toshiba has been developing since 2007. The BiCS uses a technology to stack memory cells in multiple levels by (1) stacking a gate electrode film and an interlayer dielectric film alternately, (2) making a hole that passes through all the layers and (3) embedding a polycrystalline Si channel.


The multi-level data can be stored for 10 years.

This time, the company changed the shape of the NAND string to enable multi-level operation and verify the operation at an array level.

While cells are connected to a linear (I-shaped) NAND string in the BiCS, a U-shaped NAND string is used for the P-BiCS. There are two major advantages to this structure.

 


The structure of the cell array

Properties improved by reshaping NAND string

First, because the quality of the memory cell's tunnel insulating film is enhanced, operation window and data retention capability are improved, realizing the multi-level operation. The quality of the tunnel insulating film is improved because the process of removing the tunnel insulating film at the bottom of the through-hole becomes unnecessary.

In the BiCS, the tunnel insulating film formed on the wall on the side of the through-hole is damaged during this process, often deteriorating the memory property.

Toshiba announced the method of reducing the damage by changing the material of the tunnel insulating film from SiO2 material to SiN material at the 2007 IEDM. However, the company could not ensure a sufficient memory property with the SiN material, it said.

Second, because the properties of the selection transistor and the source line used to read/write data are improved, the operation property at the array level is bolstered. In the BiCS, which has an I-shaped string, a selection transistor and a source line have to be placed on the lower part of the string.

On the other hand, in the P-BiCS, whose string is U-shaped, they can be arranged at the end (upper part) of the string. Therefore, when the string is being formed, heat of nearly 1,000°C is not applied to the selection transistor or the source line. As a result, the cutoff property of the selection transistor is enhanced, decreasing the number of read errors.

Because metal materials can be used for the source line, the writing speed can be faster than that of the BiCS. The BiCS uses a diffusion layer, which tends to be highly resistive, as a source line. When the resistance of the source line is high, the variation in threshold voltage becomes larger in the array, lowering the writing speed.

 


The process of forming the string

Mass production process required

The development group of the P-BiCS aims to establish a mass production technology for 3D-stacked NAND flash memory in two or three years as a measure to highly integrate NAND flash memory without relying on microfabrication. The P-BiCS seems to be one of the major candidates for that purpose.

"One more breakthrough is required in the processes of stacking cells and opening the through-hole to lower the cost," Hideaki Aochi, chief specialist, Advanced Memory Device Technology Dept, Center for Semiconductor Research & Development, Toshiba Corp.

For example, the hole can currently be opened through about eight levels at the same time. And the 16 levels are realized by stacking eight levels of cells twice. In the future, Toshiba might have to develop a process to form more than 16 levels at once.

 

 

 

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2. Toshiba applies germanium to 16-nm MISFET gate stack

 



 
LONDON — Toshiba Corp., claims to have developed a novel high-k dielectric gate stack with high carrier mobility that can be applied to metal-insulator-semiconductor field-effect transistors (MISFETs) in future generations of integrated circuits.

Toshiba has added a strontium germanide (SrGex) interlayer for application in MISFETs at the 16-nm node and beyond.

Current MISFET uses silicon for the channel, but physical limitations of silicon will make it difficult to obtain sufficient drive current in future scaled down MISFETs. Germanium has long been known as an alternative to silicon, offering higher carrier mobility characteristics. Development of gate stack structures for Ge-MISFETs is one of the challenges. There are reports of achieving high hole-mobility by adopting germanium dioxide (GeO2) in the gate stack insulating layer, but due to its low dielectric constant, there still remains the challenge of reducing the effective oxide thickness to 0.5-nanometers, which is required for the 16-nm node and after.

Toshiba claims to have overcomes the twin challenges of fabricating a thin gate stack while maintaining high hole mobility, by inserting SrGex as an interlayer between the high-k insulating layer and the germanium channel.

Germanium is first subject to heat surface treatment in an ultra-high vacuum, and a layer of strontium of up to ten atoms is deposited on the surface of the germanium, followed by a lanthanum aluminate high-k film. Finally, the gate stack is annealed in a nitrogen atmosphere. The SrGex layer is formed during these processes, between the high-k film and the germanium channel. The new technology realizes peak hole mobility of 481 centimeter squared per volt-second, a record high value for high-k/Ge p-MISFETs. This value is over three times than that obtained without the SrGex interlayer, and over twice the universal mobility that can be realized with silicon based on comparison with the same gate field, the company said.

Toshiba also said that a gate stack structure with an EOT of around 1-nm was formed, and that the increase in EOT by inserting the SrGex interlayer was a maximum of 0.2-nm. This suggests the possibility of further EOT scaling to 0.5-nm, either by reducing thickness of an overlaying high-k layer or adopting a high-k layer with a higher dielectric constant.

 

 

 

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3. Toshiba announces high-k/Ge gate stack technology for 16nm and beyond



Press release, June 15; Michael McManus, DIGITIMES [Monday 15 June 2009]

Toshiba has announced a significant advance in the development of a gate stack and interlayer with high carrier mobility that can be applied to advanced metal-insulator-semiconductor field-effect transistors (MISFETs) in future generations of LSIs.

The ultra-thin, equivalent oxide thickness (EOT)-scalable high-k/Ge gate stack with strontium germanide (SrGex) interlayer with high carrier mobility is a basic technology with potential for application in MISFETs at the 16nm node and beyond.

Current MISFETs use silicon for the channel, but physical limitations of silicon will make it difficult to obtain sufficient drive current in future scaled down MISFETs. Germanium (Ge) has long been known as an alternative offering higher carrier mobility characteristics, but significant technical challenges exist in implementing germanium in LSIs. Development of gate stack structures for Ge-MISFETs is one of the challenges. There are reports of achieving high hole mobility by adopting germanium dioxide (GeO2) in the gate stack insulating layer, but due to its low dielectric constant, there still remains the challenge of reducing the EOT to 0.5nm, which is required for the 16nm node and after.

Toshiba has achieved a technology that overcomes the twin challenges of fabricating a thin gate stack while maintaining high hole mobility, by inserting SrGex, a compound of strontium (Sr) and germanium, as an interlayer between the high-k insulating layer and the germanium channel.

Germanium is first subject to heat surface treatment in an ultra-high vacuum, and a layer of strontium of up to ten atoms is deposited on the surface of the germanium, followed by a lanthanum aluminate (LaAlO3) high-k film. Finally, the gate stack is annealed in a nitrogen atmosphere. The SrGex layer is formed during these processes, between the high-k film and the germanium channel.

The new technology realizes peak hole mobility of 481cm2/Volt second (Vsec), a record high value for high-k/Ge p-MISFETs. This value is over three times than that obtained without the SrGex interlayer, and over twice the universal mobility that can be realized with silicon (based on comparison with the same gate field).

Toshiba also confirmed that a gate stack structure with EOT as thin as around 1nm was successfully formed, and that the increase in EOT by inserting the SrGex interlayer was only 0.2nm at the most. This suggests the possibility of further EOT scaling to 0.5nm, either by reducing thickness of an overlaying high-k layer or adopting a high-k layer with a higher dielectric constant.

Toshiba will continue to develop the technology as an option toward implementation of Ge-MISFET to 16nm LSIs and beyond.

Cross-section of new gate stack structure applicable to Ge-MISFET for 16 nm node LSIs and beyond

Cross-section of new gate stack structure applicable to Ge-MISFET for 16 nm node LSIs and beyond
Source: Business Wire

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