Semiconductor & Patent Expert Consulting

Litigation expert consultant and patent expert witness for process, device, and circuit of  Dynamic

 Ram (DRAM), Flash  (NAND, NOR, EEPROM), and Static Ram (SRAM) Memories,

 and Microprocessor, Logic, and Analog Devices

Dave Bursky                                                                                                                                                                                                                 

Memory system designers face many challenges when implementing DRAM subsystems. As software applications grow more complex, beefier memories are needed to hold the data and run the software, while at the same time systems must operate at faster clock rates to deliver higher throughput levels. To meet those challenges, DRAM suppliers are developing faster memory architectures, denser chips and new system interfaces that will boost system throughput while allowing users to add much more memory to systems.

Systems are on the verge of the next major memory transition. At the chip level, system designers are receiving the first engineering samples of the third-generation double-data-rate synchronous DRAMs, which will offer double the data transfer speeds of today's DDR2 DRAMs. DDR3 chips will range from 800 to 1,600 Mbits/second (400- to 800-MHz clock speeds). The best DDR2 DRAMs now in production, by contrast, operate at 400 MHz, although work is progressing on an extension to the DDR2 road map to add a 533-MHz speed grade for use in systems with 1,066-MHz front-side buses. Such buses are now starting to appear in north bridge chip sets for the latest CPUs and on next-generation graphics processors.

DRAMExchange market researchers predict DDR3 production will account for about 30 percent of the total DRAM volume in 2008 and cross over with DDR2 volumes in 2009.

In addition to achieving higher speeds, DDR3 DRAMs will use a lower supply voltage: 1.5 volts, vs. the current 1.8 V. That, in turn, will lower the chips' power consumption--a critical prerequisite for reducing heat generation attributable to the devices' higher operating frequencies.

The DDR3 generation will further provide such features as an asynchronous reset pin that can be used to put the memories into a known starting state, an on-chip I/O calibration engine to tighten timing margins and support for system-level flight-time compensation to reduce skew. The chips will be available in standard and mirrored-ball-grid-array pinouts to ease front-and-back mounting on dual-in-line memory modules (DIMMs).

In early 2005, Samsung Semiconductor Inc. was the first company to demonstrate a DDR3 memory that could operate at 1,066 Mbits/s, said Tom Trill, memory product manager at Samsung. The chip was also the first DDR3 DRAM to demonstrate operation from a 1.5 V-supply.

For desktop systems and servers, Trill said, 1,066-MHz data rates will open the platforms to gigabit-rate data processing. Samsung will fabricate its chips on an 80-nanometer process.

The DDR3 road map at Qimonda AG also starts at 512 Mbits, "and we are projecting it through chip densities of up to 8 Gbits," said Ulrich Englert, director of Qimonda North America. Qimonda and Nanya Technology Corp. are jointly developing the memory architecture and process technology needed to fabricate the chips.

"Initially we expect 512-Mbit and 1-Gbit devices will be the mainstream densities. In late 2007 or 2008, 2-Gbit DRAMs will hit volume production," Englert said.

Qimonda has already delivered samples of small-outline DIMMs to ATI so that the latter can develop high-performance portable systems using the DDR3 memories, said Thomas Seifert, member of the management board of Qimonda.

Also working hard on DDR3 devices is Elpida Memory Inc., which plans to offer 512-Mbit and 1- and 2-Gbit devices, said Jun Kitano, DRAM product manager at the company. "We have already completed the development of a 512-Mbit DDR3 device using our 90-nm process node and are starting to provide early engineering samples to customers," Kitano said.

Memory designs at Micron Technology Inc. have a similar road map, with DDR3 devices slated for sampling later this year.

Speed is only one of many system considerations for system designers. Memory density and system capacity are two others, and they often move in tandem.

At the chip level, 512-Mbit DDR2 DRAMs are the workhorse devices today. They can be had in 4-, 8- or 16-bit-wide configurations and in speed grades that include 266, 333 and 400 MHz, with the 566-MHz extension in the works. Production of 1-Gbit DDR2 devices has already started at the leading DRAM suppliers--Elpida, Micron, Nanya, Qimonda and Samsung--with second-tier suppliers expected to follow in 2007.

Driving demand for these chips will be forthcoming generations of media PCs that will use larger memory spaces for video editing, transcoding and other multimedia applications. Further, the new Microsoft Vista operating system will require substantial memory to implement new operating modes, such as the Superfetch feature and Ready-boost technology to improve PC performance. In the PC world, unbuffered DIMM modules dominate because of their lower cost, but most systems can only handle two such modules before bus loading begins to have a negative effect on performance.

For servers, registered DIMMs (RDIMMs) have been the preferred module interface, and up to four 240-contact modules can typically be used on a processor's memory bus. Depending on the generation of DRAM used on the modules, this limits the maximum memory capacity per memory channel to 2 Gbytes with 512-Mbit chips, 4 Gbytes with 1-Gbit devices and up to 8 Gbytes when the forthcoming 2-Gbit DRAMs are deployed.

With 512-Mbit devices, DIMMs with capacities of 512 Mbytes can be implemented using eight byte-wide devices (plus one more byte-wide memory to add error checking and correction). By switching to a 4-bit-wide memory organization, 1-Gbyte modules can be implemented using 18 chips (including ECC). In many modules, a second row of memory chips (often referred to as the second rank) can be mounted on the module to double the capacity, thus permitting modules using 512-Mbit DRAMs to offer capacities of 1 or 2 Gbytes. With the latest 1-Gbit devices now in production, densities of 2 or 4 Gbytes are achievable using dual-rank configurations.

But even those densities aren't enough to satisfy memory-hungry servers. With samples of 2-Gbit DDR2 DRAMs emerging from suppliers such as Samsung, Qimonda and Elpida, module densities can double yet again, delivering 4 to 8 Gbytes of storage on a single DIMM. But system users will pay dearly for such high densities if they need the capacity now, since it will take several years for the 2-Gbit devices to hit mainstream production.

That's where the fully buffered DIMM enters the fray. Developed by Intel Corp., the FB-DIMM promises higher-capacity subsystems by using a serial channel interface between the host and the memory modules. Each module includes a standard interface chip referred to as the advanced memory buffer. The AMB buffers the memory arrays from the host interface so that each module presents a single load to the bus, even if it contains multiple ranks. Currently, four companies--Integrated Device Technology, Intel, NEC and Qimonda--have AMB chips, which they use in their own DIMM products or sell to other DIMM manufacturers.

The FB DIMM approach is much more pin-efficient than the RDIMM, reducing the number of module contacts from 240 on the RDIMMs to about 70 on the FB-DIMMs. The reduced number of pins allows more memory channels to be added to a system, thus allowing more modules to be addressed. Today, FB-DIMMs are available with a speed grade of 533 MHz, and by the fourth quarter Samsung expects to be sampling 667-MHz versions.

For every plus there is usually a negative, however, and for FB-DIMMs, the downside is power consumption. First-generation AMB chips consume about 5 W. Thus, FB-DIMM modules must include a heat spreader and temperature monitoring (a thermal sensor is included in the design of the AMB chip) to manage the higher power consumption.

Heat management in the overall system is also a key engineering consideration, and as such the module layout and airflow within the system become crucial design aspects.

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