1. Resistivity Reduction Enables Tungsten Scaling

As features shrink beyond 32 nm, conventional pulsed nucleation layer (PNL) will not provide the necessary resistivity performance. Tungsten nucleation and CVD fill developments can extend ALD tungsten to 2X nm features and provide needed resistivity.

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Tungsten plug fill has been the established method for filling contacts and vias in front- and back-end metallization. As feature sizes shrink and technology evolves toward 22 nm, the thinner films needed to fill these features will create challenges for memory and logic manufacturers in reducing device contact, line and via resistivity. Although some manufacturers have explored alternative metals to drive down effective contact and line resistance, tungsten is still the preferred metal because its integration into these features is well understood and its reliability established. It therefore becomes important to develop innovative tungsten atomic layer deposition (ALD) processes to overcome scaling hurdles in tungsten metallization and extend it to 22 nm and beyond.

Pulsed nucleation layer technology¹ (PNL) is a high-throughput ALD process developed to provide thin, conformal nucleation with >90% step coverage. The resulting improvement in plug fill quality with reduced seam size has extended the chemical vapor deposition of tungsten (CVD-W) process to the 3X nm technology node for memory and to the 32 nm node for logic. However, as feature sizes continue to shrink beyond 32/3X nm, conventional PNL and ALD nucleation techniques will no longer be able to provide the necessary resistivity performance to meet device requirements. Future designs in stacked capacitor DRAM will require extremely high aspect ratio (HAR) CVD-W fill capability for contacts with 17:1 to 20:1 aspect ratios.² As these HAR contacts approach 2X nm diameter openings, minimizing the volume of the feature occupied by the nucleation film will be critical to providing highly conformal plug fill and meeting resistivity requirements. Recent developments in tungsten nucleation and CVD-W fill can extend ALD tungsten down to 2X nm feature sizes and provide the resistivity and plug fill performance needed to address the challenges that arise at smaller technology nodes.

The tungsten plug fill process consists of two main steps. The first is a PNL process that consists of a sequence of pulsed gases to grow the nucleation film. The second is a CVD process that involves a continuous flow of reactant gases to fill the feature with bulk tungsten. Based on this two-step process, two approaches were used over the past decade to enhance resistivity performance. One approach reduces the CVD-W film's resistivity. The total resistivity of a tungsten film can be represented as the sum of the bulk resistivity (ρ_bulk), interface scattering (Δρ_i), surface roughness scattering (Δρ_r), and grain boundary scattering (Δρ_gb). Bulk resistivity arises from the scattering of conduction electrons with phonons. Interfacial scattering is associated with the barrier and typically is not controlled in tungsten deposition. Surface roughness scattering does not significantly increase resistivity for tungsten films below 100 nm. This leaves grain boundary scattering as a key process modulator for tungsten resistivity improvement.

The effect of grain boundary scattering on resistivity for polycrystalline films with average grain size D is estimated³ as:   

where λ is the materials-dependent electron mean free path (λ= 41 nm for W)⁴ and R is the reflection coefficient denoting the fraction of electrons reflected from the grain boundary, which contribute to higher resistivity. The relationship in the equation above shows that larger grain sizes reduce resistivity.

The low-resistivity tungsten (LRW) process was designed to reduce Δρ_gb. It incorporates a higher-temperature treatment step after the initial PNL step to create a large-grain template.⁵ Incorporating this LRW treatment step between the initial PNL step and subsequent CVD-W step can achieve a conformal large-grain tungsten film. Figure 1 compares grain size differences in the bulk film deposited between the conventional PNL film and the LRW-treated nucleation film. The bulk film's increased grain size results in less grain boundaries, reducing Δρ_gb and subsequently total resistivity.

1. Shown are 2000 Å blanket film SEM images for conventional PNL + W-CVD (a) and conventional PNL + low-resistivity tungsten + W-CVD (b).

2. Cross-sectional SEM images of 10:1 AR, 0.1 µm opening contact with CVD TiN barrier. Poor plug fill was obtained with 10 Å conventional PNL film (a), and good fill was achieved with 12 Å advanced PNL film (b).

Thin nucleation plus large grains

The two approaches to reducing feature resistivity (increasing grain size and reducing nucleation thickness) can be combined to provide additional resistivity reduction beyond what each of these two approaches can provide separately. The multi-station sequential deposition (MSSD) architecture of the tungsten deposition system has four stations in a single chamber. The architecture's temperature flexibility allows the PNLxT (lower temperature) and LRW treatment (higher temperature) processes to run sequentially in the same chamber at optimized conditions for each step, while still achieving high throughput. This process, called LRWxT, combines the benefits of PNLxT thin nucleation and the enlarged grain size obtained from the LRW treatment process (Fig. 3).

3. Differences between a conventional PNL process and advanced, low-resistivity tungsten (LRWxT). Note the thinner nucleation, additional LRW treatment layer, and the larger grain sizes in the LRWxT+CVD-W fill.

4. Measured line resistance on 90 nm comb-serpentine lines with CVD Ti/TiN liner/barrier. The four processes shown are conventional PNL+W-CVD plug fill (a), conventional PNL+LRW+W-CVD plug fill (b), PNLxT+W-CVD plug fill (c), and LRWxT (PNLxT+LRW)+W-CVD plug fill (d).

Figure 5 shows the four splits' in-trench SEMs. The inspection technique used a focused ion beam to cut the trench lines parallel to the sidewall (lengthwise). To increase the visibility of the tungsten grain boundaries, the cut samples were decorated using 100% KOH treatment at room temperature, followed by a 45-second water rinse and dry. The SEM cross-sections clearly show the grain sizes enlarged by LRW treatment and PNLxT nucleation processes. When the two approaches are combined in LRWxT, the result is the largest grain sizes of the four splits. Even with the larger grain sizes, very good fill was achieved in the LRW, PNLxT and LRWxT splits. The combined line resistance and SEM results support the inverse correlation between grain size and line resistivity, as well as the importance of thinner nucleation films. Compared with a conventional PNL process, the PNLxT and LRWxT processes result in reduced line resistivity from two different mechanisms. First, the in-trench tungsten grain size is enlarged by the LRW treatment, resulting in less electron scattering at the grain boundaries. Second, by reducing the nucleation film thickness from the typical 50 Å of conventional PNL to 10 Å of PNLxT, a higher volume percentage of CVD-W film is achieved, reducing the overall resistance of the tungsten-filled feature.

5. Tungsten texture in 90 nm trench. Shown are conventional PNL+W-CVD plug fill (a), conventional PNL+LRW+W-CVD plug fill (b), PNLxT+W-CVD plug fill (c), and LRWxT (PNLxT+LRW)+W-CVD plug fill (d).

The findings show that the PNLxT process provides optimal plug fill performance at 10 Å nucleation thicknesses. The thinner nucleation reduces the percentage volume occupied by the nucleation film, leading to lower overall contact or line resistance. The thinner nucleation approached was combined with the technique of grain-size enlargement with the LRW treatment step to form the LRWxT process, resulting in the lowest possible line resistance. The deposition system's MSSD architecture enables multi-temperature optimization for each step, allowing the system to run the LRWxT process in a single chamber. This results in low-resistance single-damascene lines and contacts that can improve performance in memory and logic circuits down to the 2X nm technology nodes and beyond.