VLSI 2008 Symposium Highlights

Nicolas Mokhoff                                                                                                                                (06/17/2008 4:00 PM EDT)
URL: http://www.eetimes.com/showArticle.jhtml?articleID=208700234


MANHASSET, N.Y. — The interdependence between process and design is in full evidence at this year's VLSI Symposia, being held June 17-20 in Honolulu, Hawaii. The Symposium on VLSI Technology straddles the Symposium on VLSI Circuits. This year the conference has two overlap days to provide a combined forum that addresses issues from processes, devices and circuits to system-level design and applications.

A few papers testify to this increasing interdependence.

In three papers, experts from the Sematech semiconductor consortium detailed new techniques for extending CMOS logic andccepts and describing how current semiconductor technologies can benefit from performance-enhancing features for future scaling needs.

"Our goal is to provide innovative and practical solutions for continued scaling of semiconductor technologies that can easily be incorporated in real-world manufacturing environments," said Raj Jammy, Sematech vice president of emerging technology.

The papers discussed leading-edge research into areas such as high-k/metal gate (HKMG) materials, and planar and nonplanar CMOS technologies. Specifically, the experts revealed a method to enable sub-1-nm EOT (equivalent oxide thickness) demonstrating scaling of SiGe PFETs at 22-nm nodes.

Meanwhile, IBM researchers revealed a prototype 45-nm six-transistor L1 and L2 cache SRAM chip set capable of reaching SRAM cell speeds beyond 6.5 GHz. This is an improvement on IBM's presentation last year at the VLSI conference held in Kyoto, where an 8-T device was detailed operating at 6 Ghz.

"The research results show that it is possible to achieve high performance for a 6-T [six-transistor] device while maintaining full functionality using several new features that enable improved writeability, stability and read/write margin analysis capability, as well as means to accurately measure internal cell speed compared to previous 6-T designs," said Rajiv Joshi, research staff member at IBM's T. J. Watson Research Center.

In addition, a newly developed super-fast Monte Carlo-based statistical analysis was used to design SRAM circuit blocks as well as arrays. The algorithms and methods employed improve Monte Carlo analysis by several orders of magnitude for such complex circuit blocks. The technique was successfully employed in predicting SRAM yields.

Power savers

Fujitsu Labs and Fujitsu Microelectronics Ltd. discussed recently developed circuit technology that can rapidly switch a power supply from off to on in less than 1 microsecond. This makes it possible to extend the "off" period, or sleep time, of a chip as a means to reduce leakage current, enabling highly integrated chips to consume less power.

Fujitsu tested the technology on a dual-core processor with 2 million gates fabbed in 90-nm process technology. The resulting restoration time was 240 nanoseconds and power-supply noise was 2.5 millivolts, compared with 20 millivolts for existing technologies, a reduction of 87.5 percent, according to the Fujitsu researchers.

Also presented was a paper on a microchip developed at the University of Michigan that uses 30,000 times less power in sleep mode and 10 times less power in active mode than comparable chips now on the market.

The Phoenix processor is geared toward sensor-based devices such as medical implants, environment monitors and surveillance equipment. The chip consumes just 30 picowatts during sleep mode. Sizewise, Phoenix is the same dimensions as its thin-film battery, which is a major achievement.

A group of U-M researchers is installing the Phoenix in a biomedical sensor to monitor eye pressure in glaucoma patients. Engineers envision that chips like this could also be sprinkled around to make a nearly invisible sensor network to monitor air or water or to detect movement.

The device defaults to sleep mode: "Sleep-mode power dominates in sensors, so we designed this device from the ground up with an efficient sleep mode as the No. 1 goal. That's not been done before," said Dennis Sylvester, an associate professor in U-M's Department of Electrical Engineering and Computer Science.

Phoenix runs at 0.5 volt.