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VLSI 2009 - Updates

Articles:

1.Toshiba announces high-k/Ge gate stack technology for 16nm / EETimes

2.Hot papers at 2009 VLSI Technology Symposium / EETimes

3.Toshiba, TSMC show different directions at VLSI Symposium / EDN

4.GlobalFoundries claims high-k advancement - EETimes

5. Thin SOI Devices Shine at VLSI Symposium - Semiconductor International

 

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2. Hot papers at 2009 VLSI Technology Symposium


 
URL: http://www.eetimes.eu/semi/217800771
 
Hot papers from this year's VLSI Technology Symposium include three nonvolatile memory advancements: Toshiba' BiCS Flash, Samsung's vertical-stacked transistor structures and Hitachi's PCRAM. Two papers on advanced logic processes include: Intel's" High-k/Metal Gate Stacks" and IBM's "32nm SOI CMOS with Highk/ Metal Gate."
 

KANATA, Ontario — I always enjoy looking through the advance programs of the Big Three chip conferences--IEDM, ISSCC and VLSI. This year is no exception. The next big event is the 2009 Symposia on VLSI Technology and Circuits scheduled next week in Kyoto, Japan.

Here are my top five tech papers from the Technology Symposium, a pillar of the upcoming VLSI Symposia. I leave the papers from the Circuits Symposium (another pillar of the VLSI Symposia) to someone with expertise in that area. Please note that I made no attempt to rank the five best papers. They are mentioned in no particular order.

Non-volatile memory

We are getting close to the tipping point for solid-state drives. I think it is more than hype as the next couple of years are bound to prove. So it should be no surprise that this list is biased toward nonvolatile memory.

If solid-state memories are to displace spinning disk technology, they need to place amongst the densest storage media, and move into terabyte territory.

In nonvolatile, it appears that the field has narrowed to two main competitors, Toshiba and Samsung, vying to replace traditional floating-gate NAND flash.

There is an option from the NAND flash camp, and it will be a form of cell stacking or 3-D memory.

Toshiba's work in this field is described in "Pipe-shaped BiCS Flash Memory with 16 Stacked Layers and Multi-Level-Cell Operation for Ultra High Density Storage Devices" which will be presented in Session 7 "Highlights" on Tuesday (June 16). BiCS is short for "Bit Cost Scalable."

Toshiba's flash paper made it to the highlight session, but Samsung took three out of four spots in the NAND Flash Memory Session. Until now, it appeared that Samsung's approach to increasing NAND flash density was to simply (okay, I obviously don't work in a fab) stack up many levels of conventional devices.

In that integration scheme, many levels of NAND flash arrays are patterned, one on top of the other, in a way resembling the die stacking in packages common today.

Samsung could be abandoning that approach, or at least diverting resources to a concept that is closer to Toshiba's paper about its pipe-shaped BiCS flash.

The Samsung paper is first up during Session 10A on NAND Flash Memory. "Novel Vertical-Stacked-Array-Transistor (VSAT) for Ultra-High-Density and Cost-Effective NAND Flash Memory Devices and SSD (Solid State Drive)" is the product of collaborative research with UCLA.

The second paper in this track is titled, "Multi-Layered Vertical Gate NAND Flash Overcoming Stacking Limit for Terabit Density Storage," and seems to address features of the same technology described in the first paper. Both papers mention vertical-stacked transistor structures and offer a new flavor for Samsung.

This technology is closer to what Toshiba has been discussing for awhile, and appears to be where flash technology will converge in the future.

The other competitor is phase change random-access memory (PCRAM).

Presently, phase change memories cannot claim a market advantage over any other proposed "replacement" for floating gate flash (whose demise had been continuously predicted since it was first introduced).

However, it's not a stretch to say that PCRAM holds the most promise among emerging nonvolatile memory types. To compete with conventional flash, it must be able to be manufactured in very low F-number cell sizes (4F or smaller) as a true cross-point memory. Hitachi will present their version in the Resistance Memory Session (2B). Their paper is titled, "Cross-Point Phase Change Memory with 4F Cell Size Driven by Low-Contact-Resistivity Poly-Si Diode."

Advanced logic processes

If you wonder what future generations of advanced logic processes will look like, chances are you will turn to Intel. As the first company to manufacture a high-K metal gate device, they have the experience to set the future direction for the high-k process

Intel's joint paper with Sematech and University of Texas at Dallas looks to be well down that road all the way to 16 nm. "Gate First High-k/Metal Gate Stacks with Zero SiOx Interface Achieving EOT=0.59nm for 16nm Application" appears in Session 3 devoted to advanced gate stacks.

Eliminating the lower dielectric constant interface layer presently used between the silicon channel and the high-K layer will be a significant step in scaling high-k. The abstract claims an equivalent physical oxide thickness of 0.59 nm, which would put it well on its way to the targets for 16 nm of around 0.50 nm. Anything less than 0.7 nm is currently a brick wall as far as the International Technology Roadmap for Semiconductors is concerned. Hence, this result is very significant.

Whether this prediction proves to be as hasty as the predicted demise of flash remain to be seen, but SOI technology often receives similar treatment.

A notable paper based on collaboration between AMD, IBM and Freescale regarding 32-nm, high-K metal gates on SOI was already recognized by the conference organizers since it appears in the highlights session.

"High Performance 32nm SOI CMOS with Highk/ Metal Gate and 0.149¼m SRAM and Ultra Low-k Back End with Eleven Levels of Copper" suggests that SOI maintains a performance advantage over bulk silicon for high-k metal gate processes at 32 nm. Achievement of this aggressive SRAM cell size and operation at 0.6V pushes this IBM club paper to the top of my list.

 

—Don Scansen is a technology analyst at Semiconductor Insights,

 

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3. Toshiba, TSMC show different directions at VLSI Symposium

 


The private debate continues among process engineers as to what will be the gate stack of the future. Intel seems to have already committed to a high-k, metal-gate path. TSMC has been publicly resolute in sticking with silicon oxy-nitride dielectrics and poly gate electrodes. Other vendors are investigating many options. But about the only public visibility of this private debate comes from the occasional paper to surface at a technical conference.

This week is bringing quite a bounty of such papers, from the VLSI Technology and Circuits Symposium in Kyoto. Two gleanings from the bounty suggest two remarkably different data points—although at two very different process nodes—for the search for the golden gate stack.

In one paper, presented Monday, Toshiba researchers described pulling out all the stops, materials-science wise, to produce a useful planar metal-insulator-semiconductor FET for use at 16 nm and beyond. The device differs in almost every possible choice of material from today's silicon-channel MOSFET with its oxide dielectric and poly gate.

The Toshiba device employs a germanium channel to get the necessary drive current in such a tiny device. This should be a source of enormous amusement to readers old enough to have suffered through Ge power transistors in the first generation of solid-state audio amplifiers. But the fact is, Ge offers the kind of very high hole mobility you need at these dimensions.

The problem is that Ge channels don't work well with currently-envisioned high-k/metal-gate gate stacks. It has been shown that you can improve the interface by embedding GeO2 in the dielectric layer, but the material has a relatively low k, and makes for an ineffective dielectric material. Toshiba researchers responded to this challenge by finding a reliable way to fabricate an atoms-thick layer of a strontium-germanium compound between the channel and a conventional lanthanum-aluminate high-k dielectric film. The Sr-Ge compound acts as an interface between the Ge channel and the conventional high-k stack. The result is a transistor with over twice the overall mobility of a comparable silicon transistor. The researchers also reported that the gate structure should be scalable beyond the 16 nm node.

Working on a more immediate problem, researchers at TSMC reported today that the company has achieved "good" yield on a 64 Mbit SRAM structure in 28 nm low-power CMOS. This is of course a qualification step on the way to introducing a commercial 28 nm process node.

The company said that this new process continues to use the conventional silicon-oxy-nitride/poly gate stack to which TSMC is so loyal. Combining aggressive oxide scaling, even more aggressive strain engineering, and who knows what else, the company has managed to squeeze at least a 25 percent improvement in speed—or alternatively a 30 percent reduction in active power—from the transistors, compared to their own 45 nm process. In the press release there was no discussion of leakage current or operating voltages, other than to say that the SRAM cell exhibited a good Vcc_min.

Of course lumbering along behind the demonstration SRAM is the full kit of a commercial process, including interconnect technology, RF and analog models, multi-oxide-thickness options, and so forth. TSMC says it is still on track to release the 28 nm node early next year.

So Intel has moved to high-k/metal-gate already. Toshiba is looking at even more radical options for two or three nodes down the line. And TSMC is demonstrating that by sheer force of will they can keep silicon-oxide dielectrics in the mainstream for at least one more generation. As the starts of horse races go, this one is pretty entertaining.

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4.GlobalFoundries claims high-k advancement





 
SAN JOSE, Calif. -- At the 2009 Symposium on VLSI Technology in Kyoto, Japan, GlobalFoundries Inc. claims that it has found a technique that enables a high-k/metal-gate transistor to scale to the 22-nm node and beyond.

The foundry vendor reported the first demonstration of a technique that allows the equivalent oxide thickness (EOT) in a high-k/metal-gate transistor to scale. The results were demonstrated through the fabrication of an n-MOSFET device with EOT of 0.55-nm and a p-MOSFET with EOT of 0.7-nm.

GlobalFoundries (Sunnyvale, Calif.) is the silicon foundry venture created by the spinoff of Advanced Micro Devices Inc.'s manufacturing operations and backed by an investment from Advanced Technology Investment Co. (ATIC) of Abu Dhabi.

The firm has a fab in Germany. It also plans a $4.5 billion, 300-mm fab in Malta in N.Y.'s Saratoga County that is expected to come online in 2012 with 35,000 wafer starts per month at full capacity.

The company is part of IBM Corp.'s ''fab club.'' The high-k/metal-gate research was performed in partnership with IBM's ''Technology Alliance.'' The ''fab club'' claims to be on track to introduce high-k/metal-gate technology ahead of all other foundries at the 32-nm node. As reported, it expects to be ready to accept 32-nm designs in the second half of 2009, with the ability to ramp production in first half of 2010.

Tokyo Electron Ltd. (TEL) is reportedly shipping its CVD tools for the high-k process within IBM's ''fab club.'' Japan's Canon Anelva Corp. is reportedly providing the PVD tools for the metal gate portion of IBM's technology platform, sources said. Canon's Anelva's PVD I-7100GT tool is installed and working in IBM, AMD, Samsung, Toshiba and others.

EOT scaling is one of the main hurdles facing the continued use of high-k/metal-gate technology at advanced nodes. ''Others have succeeded in reducing EOT, but always at the expense of device performance,'' according to GlobalFoundries.

To maintain the switching precision of a high-k/metal-gate transistor, the EOT of the high-k oxide layer must be reduced. ''GlobalFoundries and IBM have developed a new technique that overcomes this barrier, demonstrating for the first time that EOT scaling to well beyond the 22-nm node can be achieved while maintaining the necessary combination of leakage, threshold voltages, and carrier mobility,'' according to the foundry startup.

''This development could eventually provide customers with another tool to enhance the performance of their products, particularly in the fast-growing market for ultra-portable notebooks and smartphones with extended battery life,'' said Gregg Bartlett, senior vice president of technology and research and development of the foundry vendor, in a statement.

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5.Thin SOI Devices Shine at VLSI Symposium



 

 

At the 2009 Symposium on VLSI Technology in Kyoto, Japan, an IBM R&D team described fully depleted CMOS devices created on extremely thin silicon-on-insulator (ETSOI) wafers, aimed at the 22 nm node and beyond. A Hitachi team presented SRAMs fabbed on ultrathin buried oxide SOI. Both avoided ion implantation steps.

By David Lammers, News Editor -- Semiconductor International, June 18, 2009

IBM researchers went to the Symposium on VLSI Technology in Kyoto, Japan, to present a fully depleted CMOS process integration scheme for extremely thin silicon-on-insulator (ETSOI) devices, aimed at the 22 nm node and beyond.

The IBM process flow avoids implant steps, as does another thin buried oxide (BOX) SOI process flow presented at the symposium this week by researchers from the Hitachi Central Research Laboratory (Kokubunji, Japan). The Hitachi team said that in conventional CMOS on thin BOX substrates, halo implantation can cause damage to the gate oxide, especially at the gate edge. For the ultrathin BOX technology, which Hitachi calls Silicon on Thin BOX (SOTB), ion implantation was avoided to prevent damage to the oxide. Hitachi created SRAM devices that operated at 0.6 V, and said the ability to reduce the operating voltage was due to better control of the threshold voltage variations through the use of the thin buried oxide.

IBM demonstrated ETSOI devices with an active silicon layer of <2 nm.
IBM demonstrated ETSOI devices with an active silicon layer of <2 nm.

The IBM team developed prototype devices using its high-k/metal gate technology. The source/drain (S/D) and extensions were doped by an in situ epitaxial process, resulting in an implant-free flow to successfully reduce series resistance below 200 Ω/μm.  "A zero-silicon-loss process was developed to eliminate loss of the thin SOI layer during gate and spacer processes, enabling structural demonstration of sub-2 nm ETSOI," the IBM team reported.

Even without strain boosters, the IBM paper claimed a "remarkable" pFET drive current of 550 μA/μm with a 6 nm SOI channel and a 25 nm physical gate length. A 15% reduction in parasitic capacitance was achieved by a faceted raised source/drain (RSD). "Excellent electrostatics and small device dimensions render ETSOI devices suitable for the 22 nm node and beyond," the IBM team reported.

IBM's VLSI symposium presentation said fully depleted SOI with an extremely thin body has advantages, including superior control of the short channel effect with negligible dopant fluctuation. However, ETSOI poses new challenges such as extension engineering, high series resistance, increased parasitic capacitance and nearly zero tolerance of silicon loss. The performance of the pFET is of particular concern, because the strain techniques that work well for pFETs in conventional CMOS, such as embedded silicon germanium (eSiGe) stressors, are not possible with ETSOI.

Extensions are created by an RTP anneal to drive dopants in the RSD towards the ETSOI channel. (Source: IBM)
Extensions are created by an RTP anneal to drive dopants in the RSD toward the ETSOI channel. (Source: IBM)


The IBM ETSOI process flow starts by thinning the SOI wafer by thermal oxidation and wet etch, followed by high-k/metal gate creation, defined by an optimized gate etch process, which stops on the ETSOI layer. A nitride layer is deposited and etched by a partial spacer reactive-ion-etch (RIE) step to intentionally leave a thin nitride on the ETSOI. The remaining nitride on the SOI layer is removed during the subsequent RSD epi preclean with an HF acid etch to form the offset spacer, with minimal silicon loss. An epitaxy process was developed to form a faceted RSD with in situ doping. The faceted RSD reduces source and drain resistance while minimizing gate-to-S/D parasitic capacitance. Extensions are created by an RTP anneal to drive dopants in the RSD toward the ETSOI channel, the IBM team said.

"A primary advantage of our process flow," the IBM team reported, "is that S/D and extensions are formed without implantation, therefore eliminating implant-related issues such as ion straggling, amorphization of the entire ETSOI, damaging BOX and segregating dopants into the damaged BOX."

The IBM presentation in Kyoto coincides with an announcement by Soitec (Bernin, France) that it is readying its ability to manufacture SOI wafers with a thin top layer of silicon (<20 nm), with a thickness uniformity tolerance of ±5 Å.

 

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