Determining the limits of strain techniques in scaled CMOS devices
Koen Snoeckx, Peter Verheyen, and Geert Eneman, IMEC
As traditional CMOS scaling
gasps for breath, every instantly applicable solution that boosts
transistor performance is more than welcome. Strain techniques, which
introduce compressive or tensile stress in the transistor channel,
provide such an elegant method of improving charge mobility. Several
strain techniques can be integrated into standard CMOS processing
fairly easily. Moreover, combining different approaches improves the
trickiest part of using strain techniques is to find a simple solution
that works for both NMOS and PMOS transistors. Together with its
partners in the sub-45-nm CMOS program, IMEC, the Leuven, Belgium,
research center for nanoelectronics and nanotechnology, is
participating in the quest for the Holy Grail of strain engineering.
most rudimentary way to introduce stress is by applying global
strain—in other words, stress that is distributed equally over the
entire wafer. By epitaxially growing silicon on a relaxed silicon
germanium (SiGe) layer, the crystal lattice of the silicon can be
stretched, resulting in higher carrier mobility and better performance.
However, this approach has drawbacks. Several adjustments in the
process parameters are required because of the introduction of the new
substrate. What’s worse, the beneficial effect of global strain weakens
as device dimensions are scaled.
more durable solution appears to be the implementation of local-strain
techniques, which are used only on the respective PMOS and NMOS
transistors. The use of local-strain techniques has several
requirements. The first is the direction in which the stress is
introduced: parallel, vertical, or perpendicular. Each direction has a
different sensitivity to how stress affects charge mobility. The second
consideration is that NMOS and PMOS transistors can have an opposite
reaction to local strain, which reduces the possibility of finding a
simple and unified approach. Finally, each substrate and notch
direction has its own characteristic transistor behavior, which can be
a curse or a blessing when strain is applied.
avoid working in the dark, it is possible to roughly predict the
success of a local-strain technique theoretically by using the
piezoelectric coefficients as basic parameters. This type of simulation
determines the change in the electrical resistance of a material when
stress is applied to it. The result provides an indication of the
effect that stress has on charge mobility and, therefore, device
standard (100) surface wafers with a <110> notch, calculations
indicate that NMOS transistors prefer a combination of tensile stress
in the parallel direction along the channel and compressive stress in
the vertical direction perpendicular to the wafer surface. In contrast,
PMOS transistors prefer compressive stress in the parallel direction.
While tensile stress in the in-plane direction perpendicular to the
direction of the current is theoretically beneficial for both NMOS and
PMOS transistors, that effect is difficult to obtain using common
local-strain techniques. On the other hand, this stress is an important
consideration in shallow-trench isolation (STI).
Several Options for Inducing Strain in CMOS Devices
most popular local-strain technique exploits the strain induced by the
contact-etch stop layer (CESL). Using simulation methods, the effect of
tensile or compressive CESL on the stress in the channel region can be
determined. Calculations show that the stress in the parallel and
vertical directions is relatively equal in magnitude, although both
types have opposite signs, as illustrated in Figure 1. For example, a
tensile CESL results in tensile stress in the parallel direction and
compressive stress in the vertical direction. While this outcome is
suitable for NMOS transistors, it is problematic for PMOS transistors.
Figure 1: Simulation of the effect of (a) a tensile CESL with an intrinsic stress of 1 GPa and (b) an Si0.8Ge0.2
S/D on different stress directions in the center of the transistor
channel. The gate length is 40 nm. Positive stress values are tensile,
and negative values are compressive. Using common strain techniques,
the resulting stress contribution in the perpendicular direction
remains relatively small.
because stress theory is linear, variations can be accommodated. Hence,
while a compressive CESL is beneficial for PMOS transistors, it has a
deleterious effect on NMOS ones. IMEC has found that by manipulating
the stress levels in the CESL, an Ion/Ioff performance gain of 10–15%
can be obtained in NMOS transistors, while a gain of 25–30% can be
obtained in PMOS transistors with high-k/metal gate stacks, as shown in
Figure 2: Measurements from L-arrays of PMOS transistors showing the additive effect of local-strain techniques on Ion/Ioff.
Compared with the silicon reference, improvements of 30, 50, and 65%
are obtained for silicon with a compressive barrier, 15% SiGe S/D with
a compressive barrier, and 25% SiGE S/D with a compressive barrier,
To exploit the benefits of both compressive and tensile stress on one
wafer, a process flow must be found that integrates a tensile CESL on
top of NMOS and a compressive CESL on PMOS. This dual approach appears
to be the leading candidate for inducing stress in scaled CMOS devices.2 As depicted in the schematic diagram in Figure 3, the method consists of eight steps:
Figure 3: Schematic diagram of the process flow for dual CESLs. The
process involves seven more steps than the single-CESL process. A
tensile liner is deposited on top of NMOS and a compressive liner on
top of PMOS.
1. Depositing a tensile barrier.
2. Performing a lithography step to define the barrier on the PMOS.
3. Removing the etch barrier layer in the PMOS.
4. Postetch strip.
5. Depositing a compressive CESL layer.
6. Performing a final lithography step to define the compressive CESL on the NMOS.
7. Removing the etch barrier layer in the NMOS.
8. Postetch strip.
entire process requires seven additional process steps, but
experimental results indicate that despite its complexity, the dual
approach results in better performance than a single- CESL approach.
Growing SiGe in the Source and Drain Regions.
Another well-known local-strain approach is to integrate epitaxially
grown SiGe source and drain (S/D) regions. Forcing SiGe, with its
larger crystal lattice, to grow epitaxially on silicon results
primarily in compressive stress in the parallel direction.
Consequently, it can only be used for PMOS transistors.
SiGe process flow involves eight steps, which include an etch step on
the PMOS S/D regions followed by the epitaxial growth of SiGe inside
the PMOS transistor. A performance gain of 20% is achieved when 15%
germanium is applied in the source and drain, while a 40% gain is
achieved for 25% germanium.
The SiGe method is not used
for NMOS transistors. For NMOS, a similar effect may be achieved by
epitaxially growing a material with a smaller crystal lattice, such as
carbon-doped silicon. However, the current performance increase
resulting from this technique is outweighed by the complexity of the
deposition techniques required for this kind of material.
Another way to achieve stress is to combine SiGe S/D deposition with single or dual strained CESLs.3
The easiest option is to replace the neutral barrier with a tensile
one, which results in NMOS performance gains while more or less
maintaining the PMOS performance without additional process steps.
Since the tensile barrier appears to have a less degrading effect in
combination with SiGe, the need for an etch step on the PMOS is
reduced. A plausible explanation for this phenomenon is that the
topography of the SiGe S/D regions protects the PMOS channel from being
influenced greatly by the CESL layer. This combined approach results in
a 10–15% CESL improvement on NMOS and an estimated 18–38% improvement
on PMOS, depending on the limited amount of degradation.
pushing the limits, even higher performance gains are possible. The
dual-CESL approach, combined with SiGe S/D, has the most beneficial
effect on both PMOS and NMOS transistors: It results in a tensile liner
on NMOS and an SiGe layer and a compressive liner on PMOS. The downside
is that this method of inducing strain requires a total of 15 process
steps (seven for the dual CESLs and eight for the SiGe).
Stress Memorization Technique. Another way to obtain local strain is the stress memorization technique.4
A possible process flow consists of a selective amorphizing implant on
NMOS (with As+ or electrically neutral heavy atoms such as germanium),
tensile liner deposition, highly doped–drain anneal, and liner removal
before silicidation. It is hypothesized that after recrystallization,
the poly gate preserves some of the stress condition, even when the
tensile liner is removed.
The good news is that
experiments using the stress memorization technique have resulted in
performance gains of 6–8% for NMOS transistors. When combined with the
dual- CESL technique, the performance gain is even greater. The bad
news is that the technique has an extremely degrading effect on PMOS,
the reason for which is not yet understood clearly. A major effect is
that the stress-memorization technique results in an increase in the
source-drain resistance of the PMOS. Other possibilities for inducing
local strain are to manipulate the stress not only in the CESL but also
in the entire premetal dielectric stack, or to exploit the stress
introduced by STI oxide.
Turn and Repeat
The different methods for inducing local strain in CMOS devices can be used on substrates with different orientations.5,6
The use of nonstandard orientations to improve PMOS performance was
originally launched by IBM under the name of hybrid orientation
technology. The technique starts with the basic understanding that a
standard (100) substrate with a <110> notch is the worst possible
combination for hole mobility but ideal for electrons. In contrast, a
(110) substrate with <110> notch is bad for electrons but ideal
for hole mobility, making it beneficial for PMOS transistors. As
illustrated in Figure 4, IMEC has achieved improvements on the order of
40% for PMOS simply by using (110) wafers. However, unless measures are
taken to prevent it, NMOS degradation is also approximately 40%,
resulting in a net effect of zero.
Figure 4: Switching to the use of (110) wafers in place of standard
(100) wafers results in a 42% performance increase for PMOS. Unless
measures are taken to prevent it, NMOS degrades to the same degree that
PMOS improves. (The device measured had a 1.5-nm HfO2 high-k layer; PFET VDD = –1.0 V.)
related option involves using wafers with a rotated notch or simply
rotating a standard wafer by 45°. Experiments at IMEC indicate that an
improvement of approximately 20% for PMOS transistors—with no NMOS
degradation—can be achieved by switching from standard (100) wafers
with a <110> notch to (100) wafers with a <100> rotated
The entire range of local-strain techniques can
be investigated on wafers with alternative orientations, providing
process engineers with a vast array of experimental possibilities.
Simulations can enable them to make educated guesses. On (100) wafers
with a <100> rotated notch, for example, calculations indicate
that strain techniques have virtually no effect on PMOS. Substantiated
by experimental results, these calculations are bad news for those who
want to use SiGe but a blessing for those who wish to combine rotated
notch wafers with a tensile CESL. The CESL boosts NMOS performance
without affecting PMOS performance. PMOS performance improves thanks to
the rotated notch. While work on combining different substrate
orientations and rotated notches with local strain techniques is
ongoing, the complexity of the final processing will determine the most
favored options for industrial applications.
broad range of techniques is available to boost transistor performance
in scaled devices. The additive effects of these methods enable
engineers to employ them in numerous combinations depending on their
requirements. Moreover, most of the techniques—and the combinations
thereof—can be used on wafers with a variety of substrate orientations.
While fast and simple solutions such as tensile CESL on NMOS using
wafers with a rotated notch are available, they often have limited
value. More-complicated solutions such as SiGe with dual CESLs
generally result in higher performance. Whether a particular strain
technique will be used in the next generation will depend on how well
it performs under conditions of device scaling. For example, the
compressive stress induced by STI oxide will have a larger impact when
transistor dimensions decrease.
Test results indicate
that while a 65% increase in drive current is obtainable for
transistors with an SiGe S/D containing large active areas, this
improvement may decrease dramatically when transistor dimensions—such
as device width and the source-drain length—undergo further scaling.7
When the transistor width is scaled, compressive stress increases in
the perpendicular direction. While tensile stress is desirable in this
direction, compressive stress is not. When the source-drain length is
scaled, the compressive stress resulting from STI increases in the
parallel direction. At the same time, however, the amount of SiGe in
the S/D regions decreases, which also reduces the compressive stress
introduced in the channel. These examples demonstrate clearly that
research on strain effects in scaled devices must be approached with
1. P Verheyen et al., “Demonstration of Recessed SiGe S/D and Inserted Metal Gate on HfO2 for High Performance PFETs,” in Technical Digest of the International Electron Devices Meeting (Piscataway, NJ: IEEE, 2005), 907–910.
S Pidin et al., “A Novel Strain Enhanced CMOS Architecture Using
Selectively Deposited High Tensile and High Compressive Silicon Nitride
Films,” in Technical Digest of the International Electron Devices Meeting (Piscataway, NJ: IEEE, 2004), 213–216.
3. K Ota et al., “Novel Locally Strained Channel Technique for High Performance 55nm CMOS,” in Technical Digest of the International Electron Devices Meeting (Piscataway, NJ: IEEE, 2002), 27–30.
T Ghani et al., “A 90nm High Volume Manufacturing Logic Technology
Featuring Novel 45nm Gate Length Strained Silicon CMOS Transistors,” in
Technical Digest of the International Electron Devices Meeting (Piscataway, NJ: IEEE, 2003), 11.6.1–11.6.3.
5. M Yang et al., “High Performance CMOS Fabricated on Hybrid Substrate with Different Crystal Orientations,” in Technical Digest of the International Electron Devices Meeting (Piscataway, NJ: IEEE, 2003), 18.7.1–18.7.4.
H Sayama et al., “Effect of <100> Channel Direction for High
Performance SCE immune PMOSFET with Less than 0.15 µm Gate length,” in Technical Digest of the International Electron Devices Meeting (Piscataway, NJ: IEEE, 1999), 657–660.
7. G Eneman et al., “Layout Impact on the Performance of a Locally Strained PMOSFET,” in Symposium on VLSI Technology, Digest of Technical Papers (Piscataway, NJ: IEEE, 2005), 22–23.
is a scientific editor at IMEC (Leuven, Belgium), where he is
responsible for authoring and editing the organization’s technical
documents and publications. He received a master’s degree in
biochemistry from the University of Antwerp in Belgium. (Snoeckx can be
reached at +32 16 288245 or email@example.com.)
Peter Verheyen, PhD,
is a researcher at IMEC, where he is responsible for introducing strain
techniques in scaled-down technology nodes. He received an engineering
degree and a PhD degree from the Katholieke Universiteit Leuven.
(Verheyen can be reached at +32 16 281603 or firstname.lastname@example.org.)
is a researcher at IMEC, where he is working toward a PhD in
strained-silicon transistors. A research assistant for the Fund for
Scientific Research, Flanders (Belgium), he received an MS in
electrical engineering from the Katholieke Universiteit Leuven (Eneman
can be reached at +32 16 281982 or email@example.com.)