Semicyclopedia is an encyclopedia of semiconductor
terminology. It is a collection of definitions and explanations
of the technical terms and alphabet soup abbreviations commonly
accepted in the industry and academia.
Semicyclopedia is constantly
undergoing an update by STOL and also with material contributed
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- Atomic Force Microscope:
AFM is a
non-destructive surface topography analysis technique that provides
surface topographic image with a resolution in order of angstroms.
A very sharp silicon tip with a radius in the order of ~10A
is scanned close to the sample surface to get surface topology.
AFM is a powerful tool to investigate surface roughness of silicon
wafer under the gate dielectric.
- Atomic Layer Deposition:
Closely related to conventional CVD, ALD is a thin film deposition
technique that deposits very thin films with an excellent film
uniformity and conformality. Single crystal semiconductor films
such as Si, Ge and GaAS, metallic films such as tungsten and
copper, and dielectric films such as oxides and nitrides can
be deposited with ALD. Also known as ALCVD.
Chemical Vapor Deposition (see also CVD).
- A mixture of Ammonia
hydroxide, hydrogen Peroxide and water used for cleaning wafer
surface primarily to remove organic particles.
Coating: a thin layer of dielectric film, such as SiN, coated
over the wafer surface to improve lithography resolution by
reducing light scatter from the wafer surface
- ArF is a source
of an excimer laser that produces high power laser at a wavelength
- Application Specific
Integrated Circuits: As opposed to general purpose IC's, ASIC
is designed and produced for a certain specific application.
Also known as custom IC's.
- Return to Top
- Back End of the
Line: BEOL typically refers to processing steps that involve
ILD deposition, contacts and metal interconnects. See FEOL.
- BiCMOS refers to
circuits and process technology that offer both bipolar junction
transistors (BJT) and CMOS transistors on the same chip. BiCMOS
combines high current driving capability of BJT and low power
consumption of CMOS. BJT is typically used to drive a large
capacitive load while CMOS transistors are used to perform logic
functions. BiCMOS technology is more complex and more expensive
than CMOS technology, and typically serves niche markets.
- During LOCOS (local
oxidation of silicon) oxidation, two-dimensional oxidation occurs
at the edge of field oxide. As a result, oxidation extends into
the active area at the surface underneath the silicon nitride,
forming a bird's beak. Because of bird's beak, the effective
area of the active region is reduced. In the bird's beak region
of gate oxide, oxide thinning can occur due to Kooi effect (also
known as “white ribbon” effect). See Kooi effect.
- Bipolar Junction Transistor: BJT has three parts; collector,
base and emitter. In a vertical BJT, the emitter is the most
heavily doped region and the collector the least heavily doped.
“Bipolar” refers to the fact that two types of charge carriers
(electron and hole) contribute to the current flow, one being
the majority carrier and the other the minority carrier. In
an NPN BJT, electron is the majority carrier. In a PNP BJT,
hole is the majority carrier. In contrast, MOSFET is a “unipolar”
device in the sense that only one type of charge carrier is
responsible for the current flow (See MOSFET). BJT is characterized
by high current gain and high switching speed. However, its
large transistor size and high power consumption limit its use
in very large scale integration. BJT transistor effect was first
discovered by three Bell Labs researchers in 1947. This discovery
led them to winning the Nobel Prize in physics in 1956. To learn
more about the history of transistors, visit the following site.
- Barrier Metal Deposition:
Barrier metal is a thin metallic film deposited in cotacts,
via and under the metal interconnects. The purpose of barrier
metal is to prevent tungsten from reacting with material underneath
during contact fill process or to serve as a diffusion barrier
to Cu interconnects. TiN, TiW and TaN are the typical barrier
- Buffered Oxide Etch:
Silicon dioxide etching solution made of a mixture of NH4F,
HF and H2O.
Glass: BPSG oxide is typically used in the back end of the flow
in the semiconductor process to passivate the surface and to
provide smooth topology. The oxide is doped with boron and phosphorus,
which gives BPSG a gettering capability of sodium or metallic
mobile ions, and allows it to flow at a lower temperature.
tetraethylorthosilicate: BPTEOS is a BPSG film produced using
TEOS instead of silane (SiH4) that is used in a more conventional
BPSG film. BPTEOS produces void-free dense film (see also TEOS).
- Berkeley Short-channel
IGFET Model: BSIM is a MOSFET model developed by researchers
at EE department of University of California, Berkeley for MOSFET
circuit simulation. BSIM is one of the most widely used device
models for circuit simulation today.
- Barium Strontium Titanate (BaSr)TiO3: a high k dielectric
material with dielectric constant in the range of 160-600 used
in DRAM storage capacitors.
- Biased Thermal Stress:
BTS is one of the important techniques to evaluate the reliability
of dielectric film. In a BTS test, an oxide capacitor is put
under an accelerated voltage stress at a high temperature and
electrical parameters, such as flat band voltage, are measured
as stress progresses.
- Return to Top
- Charge Coupled Device:
CCD uses a packet of charge (electrons or holes) that is transferred
along the surface of semiconductor underneath the electrodes
under control of clock signals. Signal processing is performed
during charge transfer or at the output. Imaging is one of the
most important applications of CCD, such as image sensor in
the video cameras.
- Critical Dimension:
CD is the feature size defined by lithography or etch process.
Usually, it refers to the minimum feature size for a particular
layer in semiconductor processing. Feature size defined by litho
process is commonly called DICD, and the final feature size
after etch is commonly called FICD.
- Complementary MOS:
CMOS refers to circuits and process technology that provide
both P-ch and N-ch MOSFET on the same chip. In CMOS circuits,
P-ch MOSFET acts as an active load and N-ch MOSFET acts as a
pull-down driver. In a steady state, CMOS circuits consume extremely
low DC power because there is no DC current path from the power
supply (Vcc) to the ground (Vss), making CMOS an ideal candidate
for a large scale integration. In CMOS technology, P-ch MOSFETs
are formed in N-well and N-ch MOSFETs in P-well. This is called
“twin-well” CMOS technology. CMOS technology has become the
mainstream technology in today's IC industry for most of logic
and memory products (see Technology section of this Web site).
- Chemical Mechanical
Polishing (or Planarization): CMP is a semiconductor fabrication
process to planarize wafer surface. Wafer surface is grinded
by a rotating disc with chemical slurries aiding polishing process.
Metals such as tungsten, aluminum, copper, and dieletrics such
as oxide, and poly-silicon are polished by CMP. In today's advanced
CMOS process, CMP is used to planarize the surface after STI
trench fill and for ILD planarization after metal interconnect
- Crystal Originated
Pits: COP is caused mainly by voids
at the wafer surface. While epitaxial wafers are COP free, COP
is common with non-epitaxial silicon wafers. COP can
have a negative impact on gate oxide integrity. Argon-annealing
of wafers have shown a significant reduction of COP.
- Chemical Vapor Deposition
is a technique to deposit thin films on a silicon wafer. In
a CVD process, two or more gaseous materials go through a chemical
reaction in a CVD reactor chamber. As a result of chemical reaction,
dielectric molecules form and subsequently are deposited on
the wafer surface. Common dielectric films deposited by CVD
are SiO2, Si3N4, SiON. Many different types of CVD technique
are available today, based on reactor type, and process conditions,
such as pressure and plasma. These include LPCVD, APCVD, PECVD,
HDPCVD and MOCVD.
- Return to Top
- Denuded zone is
a thin layer of silicon at the top surface of a wafer that is
free of defects and contaminants. It is created after a wafer
goes through a “gettering” process. Denuded zone is where the
semiconductor devices are formed.
- Diluted HF: HF diluted
in water typically with a ratio of 100:1 (H2O:HF)
- Drain-induced Barrier
Lowering: In a short-channel MOSFET, the potential barrier between
the source and drain is lowered when drain electric field is
high and penetrates toward the source. This effect is called
DIBL. DIBL increases off-state leakage current and causes drain-to-source
punch-through. DIBL is one of the main limiting factors in the
scaling of short-channel transistors.
- Deep Level Transient
Spectroscopy: Deep level transient spectroscopy measures deep
trap levels in semiconductors. The method is based on the capacitance
change of a reverse biased diode when deep levels emit their
carriers after they are charged by forward bias pulse.
MOS: In N-ch DMOS, channel length is determined by the difference
in diffusivity of p-type dopant that forms the channel and n-type
dopant that forms the source. The region outside the p-type
channel is an n-type drift region. In DMOS, a short channel
length can be achieved with a relatively long gate length.
CMOS (also see CMOS)
today's advanced CMOS technology, gate poly-silicon for N-ch
and P-ch MOSFET is doped in n+ and p+, respectively. This is
called dual-gate CMOS. In dual-gate CMOS technology, both N-ch
and P-ch transistors operate in a surface channel mode. Surface-channel
transistors are less prone to punch-through, and are easier
to scale than the buried-channel transistors.
- Dynamic Random Access
Memory: a charge storage capacitor and an access transistor
comprise a DRAM cell. Data is stored in the storage capacitor
and is accessed through the access transistor, which is typically
an N-ch MOSFET. DRAM cell needs a periodic refreshing to keep
the data from being lost due to leakage. Data stored in DRAM
is lost when power goes off. Two main types of storage capacitors
used in the industry are stacked capacitor and trench capacitor.
- Deep Ultraviolet
Lithography: DUV refers to a lithography generation that uses
DUV light with wavelength of 248nm. DUV light is obtained from
KrF excimer laser. The name DUV is used to distinguish it from
other generations; i-line with wavelength of 356nm, g-line with
wavelength of 436nm or future generation of 193nm and 157nm.
- Return to Top
- Equivalent Oxide
Thickness: For high k dielectric, or staked gate oxide, its
electrical thickness is converted to the equivalent SiO2 thickness
for comparison purposes between different materials.
- Erasable Programmable
Read Only Memory: In an EPROM memory cell, programming is done
electrically by hot carrier injection. Electrons generated by
impact ionization tunnel through the tunnel oxide, then are
trapped in the floating gate poly-silicon. Erase is performed
with shining ultraviolet light on the memory chip, which clears
trapped electrons out of the floating gate.
- Electrically Erasable
Programmable Read Only Memory: In EEPROM, erase is performed
electrically byte-by-byte on chip. This electrical erase capability
is convenient but the memory cell size is larger than EPROM,
and as a result, EEPROM memory has lower density and higher
price than EPROM.
- Extremely Large
Scale Integration: A term used to indicate the level of integration.
ELSI refers to a higher level of integration than ULSI. Below
ULSI, in a descending order, follow VLSI, LSI, MSI and SSI.
Current flow in metal interconnects such as aluminum and copper
creates momentum transfer from electron to aluminum or to copper
atoms. This causes metal atoms to migrate in the direction opposite
to current flow, resulting in an increase in metal resistance.
In an extreme situation, voids can form in the metal interconnects
as a result of EM. EM is a serious reliability issue for metal
- Electrical Overstress:
refers to an electrical stress on semiconductor devices on a
chip that is over the electrical specification limit. Electrical
signal overshoots in the input or output pins and ESD (electrostatic
discharge) are common examples of EOS.
- Electron Beam Lithography:
a maskless lithography using electron beams to pattern photoresist.
- Electron-beam Projection
- Electrostatic Discharge:
When electrostatic charge stored on the human body or machine
tools is discharged through a semiconductor chip, it can create
damages to the circuits and devices on the chip. This is called
ESD damage. Input and output pins of IC chips are vulnerable
to ESD damages. Robustness of semiconductor chip against ESD
damage is evaluated using test methods based on several ESD
models; human body model, charged device model and machine tool
- Etch Stop Layer:
typically a thin SiN film, ESL film is deposited on the wafer
after the silicidation process of source, drain and gate poly
is complete. ESL provides necessary etch selectivity during
subsequent contact etch process.
- Extreme Ultraviolet
Lithography; EUV is one of the next generation lithography (NGL)
candidate technologies. EUV uses a light with wavelength of
around 10nm-20nm. EUV LLC is an US industry-government consortium
that carries out EUV research.
- Floating-gate Avalanche
MOS: refers to a non-volatile memory cell structure, where electrons
are generated by drain avalanche breakdown, then get trapped
in the floating gate.
- Front-end of the
line: usually refers to process steps from wafer start to completion
of transistor formation prior to first ILD deposition.
- A type of nonvolatile
memory where charge is stored in the floating gate or at the
oxide-nitride interface. Data is preserved even when the power
is off. For details, click "Memory", then see Nonvolatile
- Ferro-electric Random
- Fourier Transform
Infrared Spectroscopy: FTIR
detects impurity levels in materials used in semiconductor processing.
Infrared spectroscopy is based on transmission and absorption
characteristic of excited electrons from impurities in the sample
material. With Fourier transformation of signals, a high sensitivity
in impurity detection is achieved.
- Gate-induced Drain
Leakage: a leakage current generated by tunneling of carriers
between valence band and conduction band. GIDL occurs at the
gate-to-drain overlap region where a high drain voltage causes
a large band bending.
- Hot Carrier Injection
(see HCE, hot carrier effect)
- hot carrier effect.
Refers to the effect of high energy electrons or holes generated
as a result of impact ionization at the drain side of the channel.
These hot carriers are subsequently injected into the gate oxide,
causing device degradation. HCE is one the key reliability concerns
for the short-channel MOSFET's.
- Halo implant is
an implant with a tilt angle used to create a non-uniform channel
doping profile in a MOSFET. Halo implant is effective to control
the short-channel effect. Today's deep sub-micron transistors
typically use halo implant to improve short-channel characteristics.
- Heterojunction BJT
- High Density Plasma
- Hyrdo-peroxide Mixture
- Return to Top
- Integrated Circuits:
- Integrated Device
Manufacturer, as opposed to fabless company or foundry. IDMs
design IC products, produce them in their fabs and sell them
to the market under their brand names.
- Interlevel Dielectric:
dielectric between two different levels of interconnect
- Inter-Metal Dielectric:
same as ILD
Microelectronic Center: a research organization located in Leuven,
Belgium. IMEC perfoms contract research on advanced semiconductor
- International Semiconductor
Manufacturing Technology: an industry consortium formed to carry
out research projects for the member companies. Formerly SEMATECH,
it changed its name to ISMT after it accepted membership from
- Junction Field Effect
- Also called the
“white ribbon effect”, Kooi effect refers to the phenomena of
oxide thinning at the edge of the active area after LOCOS isolation
process. According to a model proposed by Kooi, et al., ammonia
gas generated during LOCOS oxidation diffuses under silicon
nitride LOCOS mask to the Si-SiO2 interface and forms silicon
nitride layer at the Si-SiO2 interface near the silicon nitride
LOCOS mask edge. Unless this locally nitrided region is completely
removed before a subsequent gate oxidation step, a significant
oxide thinning can occur in the gate oxide along the edge of
the active area.
- KrF is a source
of an excimer laser that produces high power laser at a wavelength
- Latch up is a self-sustaining
low impedance state between the p-type junction and n-type junction
in a p-n-p-n structure. This p-n-p-n structure acts as a pair
of coupled bipolar junction transistors (one PNP, the other
NPN BJT.) Latch up is triggered by forward-biasing one of the
p-n junctions that serves as a base-to-emitter junction. Once
triggered and if the conditions are met to sustain the latch
up, the p-n-p-n structure enters a low impedance state drawing
a large current. The latch up is sustained by a positive feedback
between the two BJT's. Latch up is a serious concern for CMOS
circuits but it can be suppressed by proper layout and process
techniques such as using guard rings, use of epi wafer or retrograde
- Large Angle Tilt
Implanted Drain. A method to form a drain and source junctions
of MOSFET using a large angle tilt implant. LATID increases
the gate-to-drain overlap, which helps reduce HCI effect.
- Local Oxidation
of Silicon: device isolation technique used in older generation
of technologies before STI was used. Silicon nitride on a wafer
surface is patterend, then the wafer undergoes oxidation. Wafer
surface area with no nitride on it gets oxidized, forming a
thick field oxide there.
- Low Pressure CVD
- Laterally Diffused
- Middle of the Line: typically refers to processing steps that
forms transistors and silcides
- Magnetically Enhanced
Reactive Ion Etch
- Metal Organic CVD
- Intel co-founder Gordon Moore's observation on technology
innovation. According to his observation, the number of transistors
on a chip doubles every two years as a result of technology
- MOSFET is for Metal-Oxide-Semiconductor
Field-Effect-Transistor. The name is derived from the vertical
structure of the transistor. Metal serves as a gate electrode,
oxide refers to a thin gate dielectric (silicon dioxide) separating
the gate electrode and silicon substrate. MOSFET is a four terminal
device: drain, source, gate and substrate. The channel is formed
at the gate oxide and silicon substrate interface by the electric
field created between the gate and substrate. As a result, current
flows between source and drain though the channel. In early
days, gate electrode was formed with aluminum, hence the name
“metal”. In today's so-called silicon gate technology, poly-silicon
is used as a gate electrode. In N-ch MOSFET, electrons flow
in the channel while in P-ch MOSFET, holes do.
- Magnetoresistive RAM
- negative bias thermal
instability is caused by hydrogen or water molecule in the gate
oxide. With very thin gate gate oxide, NBTI can be a serious
problem, especially for P-ch MOSFET. One of the theories for
the mechanism of Vt instability under negative bias at high
temperature is hole-assisted Si-H or Si-B bond dissociation
through electrochemical reaction. Positive fixed charges and
donor type interface traps are created as a result.
- Next Generation
- Oxidation Enhanced
Diffusion: During oxidation of silicon, silicon intersititials
or vacancies are created and these inturn enhance dopant diffusion
in the surrounding area.
- Optical Proximity
- Plasma Enhanced
- Plasma Enhanced
TEOS (see also TEOS)
- Plasmas induced
damage: Deposition and etch processes that rely on high density
plasma, such as PECVD, HDP oxide, can create damage to gate
dielectrics, causing reliability problems.
- Pre-Metal Dielecric
- Programmable Read
- Phase Shift Mask
- Random Access Memory
- Resolution Enhancement
channel (also retro-grade well)
- Channel doping profile that decreases in doping level going
into the silicon, then increases in doping level deep below
the channel surface.
- Read Only Memory
- reverse short-channel
effect: typically refers to an increase of MOSFET threshold
voltage (Vt) with decreasing gate length. This is opposite to
the conventional short-channel effect, where Vt decreases with
decreasing gate length.
- Rapid Thermal Anneal
- Rapid Thermal Oxidation
- Rapid Thermal Processing
- short-channel effect:
refers to the degradation of transistor performance as gate
length decreases. A typical short-channel effect is the decrease
of Vt with decreasing gate length. This effect is caused by
charge sharing between gate and source/drain
- Semiconductor Controlled
- Source Drain Extension:
a short overlap region between gate and source or drain. The
junction depth of SDE is made smaller than the heavily doped
source and drain regions to improve short-channel effect.
- Selective Epitaxial
- Self-aligned MOSFET
refers to the fact that in silicon gate technology, source and
drain are self-aligned to the gate, thus eliminating concern
for misalignment between active (source/drain) and gate.
- An industry consortium formed by U.S. companies. SEMATECH
performs advanced research for member companies. Later became
- Semiconductor Equipment
and Material Institute
- Soft Error Rate:
When an alpha particle hits a memory cell, the stored data can
be lost. The rate of this event is called the soft error rate.
- Stress-induced Leakage
- Separation by Implanted
Oxide: A method to produce SOI wafer. A high dose oxygen is
implanted into a silicon wafer. The wafer then undergoes a high
temperture thermal cycle, during which implanted oxygen reacts
with silicon forming a buried oxide.
- Secondary Ion Mass
Spectroscopy: a material composition analysis technique
An IC chip that contains high density of logic circuit and various
types of memory that provides functionality of a large system.
- Spin-on Dielectric:
- Spin-on Glass: Spin-on
glass: SOG is an oxide film deposited on a wafer during the
back end of the process flow to achieve a better planarization
of wafer surface. SOG material is a liquid solution containing
siloxane or silicate-based monomers dissolved in various kinds
of solvents in liquid form. To form SOG film, a wafer is coated
with SOG material, and is spun to get thin uniform thickness.
After curing of film to a temperature of about 300 to 400°C,
SiO2 film is formed.
devices are built in thin Si film lying over the buried oxide.
Starting material is either SIMOX or bonded wafer. PDSOI and
FDSOI, floating body effect
- semiconductor-ONO-semiconductor: A type of non-volatile memory
charge storage structure compring poly-silicon gate, ONO film
and silicon substrate. Charges injected into the oxide-nitride
interface are trapped there then later detrapped by tunneling
or carrier recombination, providing program and erase functionality.
- Solid Phase Epitaxy
- Static Random Access
Memory: two CMOS inverters are cross-coupled with two access
transistors attached to them. Unlike DRAM, refreshing is not
necessary. For details, click "Memory" and see SRAM
- Spreading Resistance
Profiling: A dopant concentration profiling technique that measures
spreading resistance as a function of silicon depth, then converts
it to the activated dopant concentration in a silicon.
- Shallow Trench Isolation:
STI is used to isolate devices on a wafer, separating the components
so that they do not electrically interfere with one another.
In STI process, a stack of thin pad oxide and a SiN film is
deposited and patterned, then silicon is etched in the patterned
area. Oxidation is then performed to grow a liner oxide over
the trench sidewall, followed by filling of trench with deposited
oxide. Oxide deposition is typically done by LPCVD or HDP. After
trench fill, oxide is polished back by CMP process. STI allows
tighter isolation, flatter surface topology and a smaller active
area loss than LOCOS. STI is almost exclusively in today's advanced
- Scanning Tunneling
- Mechanical stress from various sources in a chip causes strain
to the silicon crystal lattice. Electron and hole mobility change
as a function of magnitude and type of strain. Strained silicon
is a promising technique to enhance carrier mobility for sub-100nm
- Process simulation program developed by the researchers at
the Stanford University
Return to Top
- Technology Computer Aided Design
- Time Dependent Dielectric
Breakdown: Gate oxide reliability and lifetime is evaluated
using TDDB by applying high electric field to the oxide and
observing fail rate as a function of stress time.
- Transient Enhanced
Diffusion: TED refers to the fact dopants in the silicon wafer
diffuses at a much faster rate in very short time at the beginning
of thermal cycle.
- Transmission Electron
[Si-(OC2H5)4]: TEOS is a material commonly used to deposit oxide
film on the wafer. Oxide film deposited by CVD using TEOS offers
excellent conformality. It is liquid at room temperature but
its gaseous form is used during CVD process
- Thin Film Transistor:
TFT is formed on a thin polycrytalline film deposited on a dielectric
- Transistor Transistor
Logic: Logic IC fabricated with bipolar junction transistors
with 5V supply voltage. The name derives from the fact that
both pull-up and pull-down devices are transistors. Integration
levels range from SSI to MSI.
- Ultra Large Scale
Integration: A level of integration that is higher than VLSI
but lower than ELSI
- Ultra Shallow Junction
A specially designed
test structure which is used to measure sheet resistance of conducting
- Very Large Scale
Integration: A level of integration that is higher than LSI
but lower than ULSI
- Vertical MOS; VMOS
uses preferential etching of (100) silicon to form a V-shaped
groove at the surface of a wafer. Drain and source are formed
at the top and bottom of the V-groove, with V-groove slope used
as a gate.
- Wafer Scale Integration:
An attempt to build IC on an entire wafer