| Solid State Technology February, 2007
Author(s) : Katherine Derbyshire
The limitations of silicon are becoming more evident. Since the 90nm technology node, manufacturers have used silicon germanium (SiGe) source and drain regions, silicon carbide (SiC) liners, and other methods to strain the silicon channel. Strain engineering has already delivered substantial performance improvements, and most manufacturers’ roadmaps expect strain engineering to be the main route to performance improvement in future technology generations as well. Yet it is not clear how much more help strain can provide.
As transistors shrink, there is less room for the increasingly complex stress-applying layers that may be required. At the 2005 IEEE Electron Device Meeting (IEDM), A. Oishi and coworkers at Toshiba showed that, when cap layers are used to impose channel strain, reducing transistor spacing tends to move the point of maximum strain upward, away from the channel and into the gate stack . The channel itself will see decreasing strain, even as performance improvements call for increasing it.
Strain does not increase electron mobility as much as hole mobility, so NMOS transistors derive less benefit than PMOS transistors. In fact, Ali Khakifirooz and Dimitri Antoniadis at MIT argued, in work presented at the 2006 IEDM, that electron velocity is already approaching the ballistic limit . While PMOS performance continues to improve, Antoniadis said, “NMOS is lagging behind.” A significant performance differential between NMOS and PMOS transistors complicates circuit modeling and design, which assume the two are complementary. (Next month, part two of this series will discuss strain engineering issues in more detail.)
Meanwhile, the silicon dioxide (SiO2) gate dielectric is reaching its practical limits. In MOS transistors, the gate capacitor switches the flow of current in the channel. A voltage applied to the gate creates an inversion layer in the channel by attracting minority carriers from the bulk toward the gate dielectric interface. These minority carriers have the same sign as the source and drain doping: a PMOS transistor has p-doped source and drain with an n-doped channel, and vice versa for NMOS. Thus, the inversion layer eliminates the energy barriers at the ends of the channel, allowing current to flow. The thickness of the inversion layer depends on the capacitance of the gate. To achieve equivalent capacitance in a smaller area as the transistor scales down, the dielectric thickness must go down as well. Yet thinner dielectrics allow current to leak through. Leakage both increases the total power consumed by the circuit and blurs the difference between the on and off states of the transistor.
The dielectric thickness is usually stated as an equivalent oxide thickness (EOT): the thickness of an SiO2 layer with the same capacitance. Increasing the dielectric constant increases the physical thickness used for a given EOT, thereby reducing leakage.
Nitrogen doping of SiO2, for instance, has allowed gate thickness scaling to an EOT of about 1.2nm with acceptable leakage, but this value appears to be the practical minimum. Below it, leakage exceeds the permissible 10-25% of total circuit power. The need to control gate leakage in turn limits scaling of the gate length: to avoid short channel effects, the gate length should ideally be about 40× the thickness of the channel inversion layer. Yet without thinner gate oxides, the thickness of the inversion layer cannot scale any further .
Click here to enlarge image
TEM image of Ge-channel PMOS transistor with 0.125μm (125nm) physical gate length. (Image courtesy of IMEC)
Intensive research is underway to identify an alternative gate dielectric. A high dielectric constant (k) material would give more capacitance in a physically thicker layer, thereby reducing leakage current. Several viable alternatives for the NMOS gate electrode and dielectric have been found. High-k PMOS transistors remain a challenge, however. Polysilicon gates use doping to place the gate work function near the appropriate edge of the band gap for PMOS or NMOS transistors. Polysilicon gates are not compatible with high-k dielectrics, but the band-edge metals needed for PMOS transistors all raise significant integration challenges. As with strain engineering, manufacturers must consider the possibility that NMOS and PMOS transistors will deliver significantly different performance. (Part three of this series will discuss high-k dielectrics in more detail.)
So what’s a device engineer to do? Well, if you’re limited by carrier mobility, there are plenty of semiconductors with higher mobility than silicon. If you’re going to have to abandon the SiO2 gate dielectric, then the best reason for staying with silicon goes away, too. Maybe it’s time to look at other materials.
Germanium (Ge) is one option. Of course, Ge has a long history in the semiconductor industry. As discussed in the article “Change and silicon: the only constants” (p. 57), the original Bell Labs transistor depended on Ge, as did the Texas Instruments integrated circuit demonstrated by Jack Kilby. It has electron mobility of 3900cm2/V-sec, compared to 1350 cm2/V-sec for silicon, while Ge’s hole mobility of 1900cm2/V-sec is the highest of any known semiconductor. Germanium readily forms an alloy with silicon, silicon germanium (SiGe), which has been used in strain engineering for years. As Suresh Venkatesan, senior director of CMOS platform device development at Freescale Semiconductor explains, SiGe integration and selective deposition of SiGe are “known arts,” requiring no new process tools. Increasing the Ge concentration offers a relatively clear migration path from pure silicon channels, through SiGe, to pure Ge.
In general, the same integration schemes are available whether the channel is composed of SiGe or pure germanium. Mobility increases as the fraction of Ge increases. However, increasing the Ge concentration also increases the lattice mismatch between the channel and the underlying silicon substrate. While the resulting strain may be desirable, pure Ge layers may need a graded SiGe transition layer to prevent dislocation formation. In practice, early devices are likely to depend on SiGe, with Ge concentration increasing as the industry gains familiarity with the material.
The first obstacle to germanium’s re-introduction is the one that forced the industry to turn to silicon in the first place-the lack of a passivating native oxide. Germanium’s native oxide, GeO2, is unstable and water-soluble. Its only virtue is that it is easy to remove, preparing the surface for dielectric deposition.
One of the simplest integration routes reduces the germanium passivation problem to the solved problem of silicon oxidation. After Ge channel deposition, Paul Zimmerman and coworkers at IMEC, Leuven, Belgium, used a thin silicon cap-four monolayers or so-to stabilize the Ge surface (see figure). Dielectric deposition then proceeded exactly as it would in silicon-based transistors. The silicon cap layer, with its native oxide, gave a clean interface for deposition of a high-k dielectric. Because the silicon layer was so thin and the resistance of Ge was significantly lower, the drive current flowed through the Ge layer, gaining the mobility advantage it offered.
The IMEC team presented at the 2006 IEDM with this approach using a hafnium oxide (HfO2) gate dielectric and bilayer tantalum nitride (TaN)/titanium nitride (TiN) gate electrodes. Nickel germanium source and drain contacts completed the structure. PMOS devices with channel lengths down to 0.25μm (250nm) had good current-voltage characteristics, with sharp on-off transitions. Devices with shorter channels suffered from gradually increasing short channel effects, which the IMEC team attributed to the omission of the HALO implants routinely used for short channel control in silicon devices. Short channel devices also showed significant mobility degradation. However, this appeared to be due to external contact resistance, not to the transistors themselves .
Though using a silicon cap layer simplifies germanium integration, it is probably not the ultimate solution. Adding silicon and SiO2 to the gate stack increases the effective thickness of the gate dielectric. As EOT scales below 1.5 or 1.2nm, even a few monolayers can make a significant difference. If possible, manufacturers would prefer a dielectric that can be deposited directly on Ge.
The search for such a dielectric begins with rapid thermal nitridation of GeO2. According to Chi On Chui and coworkers at Stanford University, nitrogen appears to accumulate at the Ge interface, reducing the number of interface traps and improving interface stability. As with SiO2, nitrogen increases the dielectric constant, apparently by increasing Ge and oxygen coordination in the network structure. Studies of MOS capacitors-not functioning transistors-found an asymmetric distribution of interface traps, with a higher trap level in the upper part of the Ge bandgap. Chui suggests that this asymmetry may help to explain the asymmetric mobility degradation observed in n-channel relative to p-channel MOSFETs with GeOxNy dielectrics .
Even more important than the primary dielectric properties of GeOxNy, however, is the ability of the material to provide an interface for deposition of other materials. Hafnium oxide for instance, has a dielectric constant of about 20, but does not passivate the Ge surface. Adding a GeOxNy integration layer improves interface quality and reduces leakage, but at the cost of increased equivalent thickness.
Another alternative, zirconium oxide (ZrO2), has a dielectric constant of 30 and is stable in the presence of Ge. In MOS capacitors based on zirconium oxide, Chui said, it is possible to reduce equivalent thickness by omitting the interface passivation layer. 
A second issue for germanium-based transistors is the material’s smaller bandgap of 0.7 eV, compared to 1.1 eV for silicon. The smaller gap effectively lowers the energy barrier between n-type and p-type materials, facilitating band-to-band tunneling and leakage at junctions. This leakage may ultimately limit the scalability of Ge transistors. Fortunately, simulation studies presented at the 2006 IEDM suggest that strain modifies the channel’s bandstructure and can help control leakage in Ge channels. This effect is seen in silicon as well, but Ge’s higher intrinsic mobility seems to allow more latitude for strain engineering .
The many alternative materials being considered for the 32nm technology node make predictions difficult. As Freescale’s Venkatesan put it, there’s an “alphabet soup” of alternatives, and no single solution has shown that it will provide both high performance and low power consumption, for both PMOS and NMOS devices. Though SiGe channels may be part of the solution-Freescale plans to integrate the material, Venkatesan said-they are just one more knob that device engineers can turn. The “best” device will be the one that meets the needs of a particular circuit.
Lithographers have long faced a trade-off between mask cost and equipment cost. More expensive masks may allow fabs to get by with less expensive equipment, so the economic equation depends on the volume and cost constraints of a particular design. Similarly, circuit designers can use many different techniques to squeeze out the last bit of performance, but many of these techniques add considerable process complexity and yield risk. Low-power, high-volume parts may find advantages in simplicity instead. The upcoming articles in this three-part series will review the trade-offs in more detail.
- A. Oishi, et al., “High-performance CMOSFET Technology for 45nm Generation and Scalability of Stress-induced Mobility Enhancement Technique,” IEDM Tech. Digest, 2005.
- A. Khakifirooz, D.A. Antoniadis, “Transistor Performance Scaling: The Role of Virtual Source Velocity and its Mobility Dependence,” IEDM Tech. Digest, 2006.
- S.E. Thompson, et al., “In Search of ‘Forever,’ Continued Transistor Scaling One New Material at a Time,” IEEE Trans. Semi. Mfg., Vol. 18, p. 26, 2005.
- P. Zimmerman, et al., “High-performance Ge pMOS Devices Using a Si-compatible Process Flow,” IEDM Tech. Dig., 2006.
- Chi On Chui, Fumitoshi Ito, Krishna C. Saraswat, “Nanoscale Germanium MOS Dielectrics-Part I: Germanium Oxynitrides,” IEEE Trans. Elec. Dev., Vol. 53, p. 1501, 2006.
- Chi On Chui, et al., “Nanoscale Germanium MOS Dielectrics-Part II: High-k Gate Dielectrics,” IEEE Trans. Elec. Dev., Vol. 53, p. 1509, 2006.
- T. Krishnamohan, et al., “Theoretical Investigation of Performance in Uniaxially- and Biaxially-strained Si, SiGe and Ge Double-gate p-MOSFETs,” IEDM Tech. Dig., 2006.
Katherine Derbyshire received her engineering degrees from the Massachusetts Institute of Technology and the U. of California, Santa Barbara. She is the founder of consulting firm Thin Film Manufacturing, firstname.lastname@example.org, http://www.thinfilmmfg.com.
Solid State Technology February, 2007
Author(s) : Katherine Derbyshire