DRAM is almost synonymous to semiconductor memory
because of its huge market size. Demand for DRAM has exploded since
the introduction and proliferation of personal computers. Today, DRAM
commands a market size of ~$30B, roughly 20% of the total annual semiconductor
is known for its boom-and-bust cycle, typically in a 4-year period.
Boom-and-bust cycle has been particularly brutal for DRAM. Because
of this, a dramatic shift in DRAM power base and the consolidation
of DRAM manufacturers took place over the past 30 years. Currently,
Samsung and Hynix of Korea, Elpida of Japan, Infineon in Europe
and Micron in the U.S. hold the lion’s share of the merchant
DRAM market. IBM, another big DRAM manufacturer, serves its own
The DRAM cell consists of an access transistor and a charge storage
capacitor. The simple cell structure renders itself to a small cell
size, resulting in a cost-effective high- density semiconductor data
storage element. Although simple in its cell structure, requirements
for electrical characteristics, process capability and continuous scaling
are rigorous and challenging.
The operation of DRAM cell requires extremely low leakage current.
Transistor sub-threshold leakage, junction leakage and capacitor dielectic
leakage current must be kept low to meet the cell refresh requirement.
Not only the well-engineered transistors and storage capacitors, but
also a good control of defects is crucial to meet the leakage requirement.
Technical innovation in DRAM continued over the past 30 years in the
industry, enabling DRAM scaling into sub 100nm regime today. A big
milestone in DRAM density of one gigabit DRAM was reached in the middle
Two types of storage capacitor architecture exist today: stacked capacitor
and trench capacitor. The stacked capacitor cell is used by Samsung,
Micron and Elpida (Hitachi/NEC). The other camp using trench capacitor
cell is IBM, Infineon, and Toshiba.
The following summary
describes the major milestones in DRAM technology, chronicled from
the International Solid State Circuits Conference (ISSCC) from 1982
to 2003. See below for the advancements in DRAM that the industry
has achieved in a relativley short time span of a little more than
The title of one informal
evening discussion session says, quite seriously, “Is there
life after 64K?” Fundamental issues in circuit design and
process technology at 64Kb and higher density were discussed. Most
panelists had an optimistic view that problems could be overcome.
256Kb development is at a maturing stage. NMOS 256Kb by Fujitsu with
2.5um NMOS triple poly process, 256Kb by NEC on 1.3um double poly process,
256Kb by Mitsubishi on 2um process, 256Kb by Motorola, 256Kb by Toshiba
with 2um double poly process. Intel shows off industry-first CMOS DRAM
with 64Kb on 1.2um process.
1Mb DRAM appears. 1Mb
by NEC on 1um NMOS double poly process, 1Mb by Hitachi using NMOS
process with trench capacitor. Intel presents 256Kb CMOS DRAM. Stacked
capacitor concept debuts in a paper by Fujitsu.
1Mb DRAM flourishes. 1Mb
by NEC on 1um NMOS process with trench capacitor, 1Mb by Mitsubishi
with planar capacitor on 1.2um NMOS process, 1Mb CMOS DRAM by Mostek
on 1.2um process, 1Mb DRAM by Toshiba on 1.2um NMOS process, 1Mb
by IBM using 1um NMOS process, 1Mb by Fujitsu using 3-D stacked
capacitor with triple poly concept.
CMOS 1Mb DRAM becomes
mainstream. 4Mb DRAM debuts. TI describes 4Mb DRAM with trench capacitor
where access transistor is also vertically integrated into the trench.
NEC and Toshiba respectively show their versions of trench capacitor
cell in 4Mb DRAM. Design rules ranges from 0.8um to 1.2um.
4Mb DRAM takes the center stage. Mitsubishi and IBM describe 4Mb
CMOS DRAM using trench capacitor based on 0.8um design rule.
Experimental 16Mb DRAM
is presented by Matsushita (trench capacitor), Toshiba (trench capacitor),
and Hitachi (stacked capacitor).
More 16Mb DRAMs appear
using 0.5um – 0.6um design rules: Mitsubishi (stacked capacitor),
Toshiba (stacked trench capacitor), NEC (stacked capacitor).
Relatively quiet year
in DRAM. 4Mb DRAM from Fujitsu and Mitsubishi and 16Mb DRAM from
IBM were all. 16Mb DRAM from IBM was fabricated on 0.5um CMOS technology
using trench capacitor cell.
Era of 64Mb DRAM begins.
Four 64Mb DRAM, all in experimental stage, were introduced by 4
Japanese companies, illustrating their dominance in DRAM technology.
Matsushita, Mitsubishi and Fujitsu built their 64Mb on 0.4um CMOS
process using stacked capacitor cell. Toshiba used trench capacitor
cell and 0.4um CMOS process to fabricate its 64Mb DRAM.
NEC describes 64Mb DRAM
using 0.4um CMOS process and stacked capacitor cell. Not much DRAM
First 256Mb appears. Hitachi
described an experimental 256Mb fabricated on 0.25um CMOS process
with stacked capacitor cell. 256Mb from NEC was also built on 0.25um
CMOS process with stacked capacitor cell.
More 256Mb chips appear
from 3 Japanese companies; Matsushita, Mitsubishi and Oki, each
presented 256Mb DRAM built on 0.25um CMOS process with stacked capacitor
Era of giga-bit DRAM begins.
Hitachi describes an experimental 1Gb DRAM fabricated on 0.16um
CMOS process with stacked capacitor cell. NEC fabricated its 1Gb
DRAM on 0.25um CMOS process with stacked capacitor cell. Signaling
an arrival of Korean DRAM manufacturers, Hyundai (currently Hynix),
describes 256Mb DRAM built on 0.3um CMOS process using stacked capacitor
1Gb SDRAM by Mitsubishi
on 0.15um CMOS process, 1Gb DRAM by Samsung on 0.16um CMOS process
with stacked capacitor cell.
1Gb DRAM by Oki on 0.16um
CMOS process with stacked capacitor cell, 4Gb DRAM by NEC on 0.15um
CMOS process with 4-level storage cell.
Fujitsu describes 1Gb
synchronous DRAM fabricated with 0.18um CMOS process with stacked
Three companies delivered DDR SDRAM
at 1Gb density. Samsung fabricated 1Gb on 0.14um CMOS process using
stacked capacitor cell. NEC’s 1Gb DRAM is fabricated on 0.18um
CMOS with stacked capacitor cell. IBM’s 1Gb DRAM is fabricated
on 0.18um CMOS process with trench capacitor cell. Effort is focused
on improving data rate rather than bit density.
There’s no advancement
in DRAM density. Efforts are focused on DRAM architectures and embedded
A new milestone in the
DRAM density is reached by Samsung. Samsung presented 4Gb chip on
0.10um CMOS process with stacked capacitor cell using Ta2O5 as capacitor
No breakthrough reported
in technology innovation or density improvement. DRAM is more focused
on design and application issues.
DDR2 and DDR3 SDRAM design
is the main theme. Process technology used in these chip design
is 0.10um or 0.13um CMOS.
Among several types of non-volatile memories (EPROM, EEPROM, mask
ROM, flash memory, etc), flash memory represents today’s mainstream
nonvolatile memory. Thanks to its usage in consumer products such as
cellular phones and digital cameras, flash memory saw an explosive
growth in demand in recent years. This growth trend will continue as
application of flash memory becomes more pervasive.
Flash memory evolved from EPROM and retains its floating gate and
tunnel oxide architecture. By reducing the tunnel oxide thickness under
the floating gate that typically ranges from 300A to 400A in EPROM
to a 90A-100A range, electrical erase through FN tunneling became possible
and flash memory that we see today was realized.
Wide acceptance of flash
memory is due to its in-system program and erase capability. In
contrast to erasing the whole chip off the system with UV light
as is done with EPROM, flash memory is erased electrically by each
sector while residing in the system.
Toshiba demonstrated the
first flash memory chip at the 1985 ISSCC. The chip had 256Kb density
and the cell was erased through poly-to-poly tunneling. (Check erase
mechanism, it could be poly-to-poly tunneling.) As flash technology
evolved, two main flash cell array architectures have emerged. The
traditional NOR flash memory offers high speed and high reliability.
The late comer NAND flash memory offers high density and low per-bit
cost. Today, 256Mb NOR flash memory and 1Gb NAND flash memory are
in volume production.
For NOR type flash memory,
Intel and AMD are the two market leaders. Recently, NAND flash memory
is enjoying growing popularity in consumer products such as digital
camera and cell phone. Samsung and Toshiba are the dominant market
leaders for the NAND flash memory.
Along with continuous
effort to scale down the flash memory cell, effort to increase bit-density
at a given generation has resulted in a realization of multi-level
cell (MLC) and dual-bit cell architecture.
In MLC, pioneered by Intel,
doubling of bit density is realized by storing different amount
of charges in the floating gate for the three programmed states.
Intel currently delivers 256Mb NOR StrataFlash chip based on MLC.
On the other hand, in the dual-bit cell architecture by AMD, called
Mirror Bit technology, two bits are stored in a SONOS-based cell
-each bit stored at each end of the channel of the cell transistor.
AMD has sampled 512Mb flash memory using Mirror Bit technology.
In parallel with scaling
the conventional Si-based flash technology, industry is actively
pursuing alternative non-volatile memory technologies for the future.
These include FRAM (Ferroelectric memory), MRAM (magnetoresistance
memory), Calchogenic memory, and memory based on polymer. Some are
more mature and/or promising than others but at this time it is
hard to say which or any of these is a legitimate threat to or an
eventual winner over the existing Si-based flash memory.
Below we show the evolution
of non-volatile memory technology by chronicling the major milestones
since 1980 as they appeared in ISSCC. After Toshiba’s first
demonstration of flash memory in 1985, development effort in the
industry on non-volatile memory technology gradually shifted from
EPROM to flash memory during 1985–1991 period. From 1992,
industry effort has been mainly on flash memory technology development.
Intel presents 64Kb EPROM.
It had 700A tunnel oxide and was fabricated with 3.5um design rules.
Motorola presented 16Kb EEPROM built on 4um NMOS process.
Little activity seen on
Motorola presents 32Kb
EEPROM and 128Kb EPROM is presented by Intel.
Signetics shows 64Kb EPROM
built on 3um CMOS process.
A very productive year
for nonvolatile memory. EPROM technology development heats up as
EPROM process migrates from NMOS to CMOS. NEC demonstrates the first
1Mb EPROM using 1.2um CMOS process with 300A tunnel oxide. Also
presented are 512Kb EPROM from AMD fabricated with 1.7um NMOS process
and 256Kb EPROM from Seeq using 1.5um CMOS process and 256Kb CMOS
EPROM from Toshiba. Seeq presents 64Kb CMOS EEPROM.
Toshiba sets a milestone
by presenting 256Kb flash EEPROM based on 2um triple poly CMOS process.
This is the 1st flash memory in the industry. Hitachi presents 1Mb
CMOS EPROM using 1.3um process, while Intel’s CMOS EPROM is
at 256Kb density using 1.5um process.
AMD presents its 1Mb EPROM
using 1.5um CMOS process.
Toshiba debuts the 1st
4Mb EPROM using 0.8um CMOS process. 1Mb CMOS EPROM’s are presented
by Fujitsu and TI, respectively, using 1.5um process. Seeq demonstrates
128Kb flash EEPROM based on double poly CMOS process.
Intel comes out strong
with 4Mb EPROM built on 1um CMOS process with 250A tunnel oxide,
and 256Kb CMOS flash EEPROM based on 1.5um double poly process.
Flash memory development
effort accelerates. TI presents 256Kb CMOS flash EEPROM. 1Mb flash
EEPROM from Seeq is fabricated on 1.5um CMOS double poly process.
1Mb flash memory from Intel was built on 1um CMOS double poly process.
Toshiba sets another milestone by introducing the 1st NAND flash
memory with 4Mb density using 1um CMOS process.
NEC demonstrates the 1st
16Mb EPROM with 3.6um**2 cell size, resulting from 0.6um CMOS process
with STI isolation. Hitachi shows 1Mb flash EEPROM based on 0.8um
CMOS process. Its cell size is 10.4um**2 and the thickness of tunnel
oxide and inter-poly oxide are 100A and 300A, respectively.
16Mb flash EEPROM from
Mitsubishi uses 0.6um CMOS process and features cell size of 3.6um**2,
tunnel oxide and inter-poly oxide thickness of 100A and 200A. 16M
EPROM from Toshiba was fabricated on a 0.6um N-well CMOS process
with cell size of 3.85um**2. Now flash memory and EPROM are on an
equal footing in terms of cell size and density.
The 1st flash memory operating
on a single supply voltage appears; 4Mb flash memory by Toshiba
and 16Mb flash memory from NEC. NEC’s 16Mb flash memory operates
on Vcc of 5V. It is fabricated on a 0.6um triple-well CMOS process
with cell size of 3.4um*2, and tunnel oxide and inter-poly oxide
thickness of 110A and 180A, respectively.
Little new development
reported in nonvolatile memory technology.
NEC raised the bar of
flash memory density by presenting the 1st 64Mb flash operating
on 3.3V. It is built on a 0.4um twin-well CMOS process with cell
size of 1.65um**2, tunnel oxide and inter-poly oxide thickness of
75A and 130A, respectively. Intel presents 16Mb flash memory fabricated
on a 0.6um twin-well CMOS process with cell size of 3.6um**2, tunnel
oxide and inter-poly oxide thickness of 100A and 180A, respectively.
To commemorate 10th anniversary
of the development of flash memory, an entire session is dedicated
to the flash memory for the first time in this year’s ISSCC.
Momentum has completely shifted from EPROM to flash memory. 3.3V
supply voltage has become the mainstream. Various cell architectures
are presented. These include 16Mb DINOR flash by Mitsubishi with
cell size of 1.35x1.4um**2, 32Mb AND flash by Hitachi with cell
size of 1.8x0.9um**2 built on 0.45um triple-well CMOS process, 34Mb
serial flash by SanDisk, 32Mb NAND flash by Samsung with cell size
of 18.3x1.4/16um**2 processed with 0.5um CMOS triple-well process,
32Mb NAND flash by Toshiba built on a 0.425um CMOS twin-well CMOS
process memory with 32Mb density (physically 16Mb) fabricated on
a 0.6um twin-well CMOS process with cell size of 3.6um**2.
Flash memory takes momentum.
128Mb NAND flash from Samsung uses 0.4um triple-well CMOS process
with cell size of 1.1um**2. 64Mb AND flash by Hitachi is built on
a 0.4um triple-well CMOS process with cell size of 1.28um**2. NEC
shows 64Mb flash with a 4-level cell (2 bits per cell) fabricated
on a 0.4um triple-well CMOS process with cell size of 1.47um**2.
128Mb AND flash from Hitachi operating at Vcc=2.5V is built on a
0.25um CMOS process with cell size of 0.4um**2.
No major progress in flash
Flash memory development
goes dormant 2 years in a row in terms of density.
256Mb multi-level AND
flash 0.25um CMOS by Hitachi, 256M NAND flash by Toshiba 0.25um
CMOS with STI cell=0.29um**2 BL pitch is reduced to 2.2F from 3F
by STI, 1.8V DINOR flash 16Mb by Mitsubishi 0.25um triple-well CMOS
STM describes 1.8V 64Mb
NOR flash with 4-level cell using 0.18um triple-well CMOS process.
Toshiba’s 1.8V 32Mb NOR flash is fabricated on a 0.25um CMOS
process with cell size of 0.49um**2.
Samsung presents 1Gb multi-level
(MLC) NAND flash (2 bits per cell) operating at 3.3V. Hitachi presents
512Mb 1.8V AND flash using 0.18um CMOS process and a multi-level
Toshiba and Samsung crack
1Gb density barrier in NAND flash. 1Gb NAND from Toshiba is built
on a 0.13um CMOS process. Samsung’s 1Gb NAND flash operates
at 1.8V and is fabricated on a 0.12um CMOS process. Saifun describes
a new type of flash memory based on SONOS technology, which Saifun
calls NROM. Saifun’s 512Mb NROM is built on a 0.17um triple-well
CMOS process with cell size of 0.082um**2 with 2 bits stored per
Intel reports 1.8V NOR
flash with 128Mb density with MLC fabricated with 0.13um CMOS process.
1Gb AND flash is reported by Hitachi using MLC and 0.13um CMOS process.
Samsung reports 2Gb NAND flash, the highest density NAND flash to
date, using 90nm CMOS process.
Advantages of SRAM are high speed, low power consumption, ease of
use (no need for cell refreshing), a good cell operating margin and
cell stability. Major drawback of SRAM is its cell size and because
of it, low density and higher cost per bit compared with DRAM.
MOS SRAM was first developed in 1969 using 12um PMOS technology with
gate oxide thickness of 1100A with cell size of 33 mil**2. The next
major development came when SRAM was built in NMOS technology. Two
pairs of N-ch enhancement transistors were cross-coupled as a flip-flop
with each pair having N-ch enhancement transistors as pull-up and pull-down
devices. The N-ch enhancement transistor used as a pull-up load was
later replaced by a depletion transistor.
SRAM density has improved
significantly when industry adopted a 4-transistor cell with poly-Si
load using double poly-Si SRAM technology. While poly-Si load cell
achieves a small cell size, it is susceptible to soft error caused
by alpha particles. Because of this, data retention becomes a problem
at very high density for poly-Si load SRAM. Low standby current
also becomes a challenge for poly-Si load cell at a very high density.
Data retention problem
associated with poly-Si load cell is alleviated in a 4-transistor
cell with thin film transistor (TFT) load. SRAM with PMOS transistor
formed in upper poly-Si layer as a TFT load achieves low power,
small cell size and good data retention (SER) at very high density.
Today’s advanced highdensity SRAM uses 4-transistor cell with
PMOS TFT load.
A full CMOS 6-transistor
SRAM cell has ideal SRAM characteristics except for the cell size.
The 6-transistor cell consumes very low power, is very stable and
tolerant to alpha particle. However, the cell size is typically
twice as large as poly-Si load cell. Because of this, a full CMOS
6-transistor SRAM is used as an embedded memory in logic chips as
cache memory rather than as a stand-alone memory product. It is
used as a technology development vehicle and also an important figure
of merit for logic technology.
Described below is the
evolution of SRAM technology since 1980. Major SRAM milestones are
listed as they appeared in ISSCC.
16Kb 5V CMOS SRAM with
depletion mode JFET load is presented by Hitachi with cell size
of 28x32um**2. Toshiba presents 16Kb CMOS SRAM with cell size of
33x34um**2 using 2um CMOS double poly process. Matsushita presents
the 1st 64Kb 5V SRAM with cell size of 6x19um**2.
64Kb 5V SRAM by NEC is
made of 6-transistor with depletion load, has cell size of 11x26.5um**2
and is processed with 1.5um double poly process. TI presents 16Kb
NMOS SRAM using 2.5um NMOS double poly process.
Intel presents 64Kb NMOS
SRAM with poly-Si resistor processed with 1.5um NMOS process featuring
15x21.75um**2 cell size. Hitachi presents 64Kb CMOS SRAM with poly-Si
load with cell size of 13.5x22.5um**2 using 2um CMOS double poly
process. 64Kb CMOS SRAM by Toshiba is processed with double poly
2um CMOS process and features 4-transistor poly-Si load with cell
size of 15x19um**2.
64Kb full CMOS SRAM by
Mitsubishi is processed with 2um CMOS process and uses 6-transistor
cell of 21x24.5um**2. NEC also presents 64Kb CMOS SRAM processed
with 2um CMOS process with cell size of 18.4x19.9um**2.
Double poly CMOS process
with poly-Si load cell becomes the standard process for SRAM technology.
Toshiba presents the 1st 256Kb 5V CMOS SRAM processed with 1.2um
double poly CMOS process that features poly-Si load cell with the
size of 11x13.5um**2. 64Kb 5V SRAM by NEC is processed with 1.5um
CMOS double poly process and uses poly-Si load cell with 14.9x19.3um**2
size. 64Kb 5V SRAM by Hitachi uses 1.3um CMOS process and features
8x16um**2 cell with poly-Si load.
Hitachi presents 256Kb
5V CMOS SRAM using 1.2um CMOS double poly process with poly-Si load
and the cell size of 94.7um**2. 256Kb 5V SRAM by NEC is processed
with 1.2um CMOS double poly process and features cell size of 7.4x12.1um**2
with poly-Si load.
256Kb full CMOS SRAM is
presented by Sony. It is processed with 1um single poly CMOS process
and cell size is 10.6x13.2um**2.
This year marks the beginning
of mega bit SRAM. Four Japanese companies introduce their 1Mb SRAM.
1Mb SRAM by Sony is processed with 1.0um double-poly, double-metal
CMOS process and features 6.4x11.6um**2 cell with poly-Si load.
1Mb SRAM by Hitachi uses 0.8m triple-poly CMOS process and has a
poly-Si load cell with the size of 5.2x8.6um**2. 1Mb SRAM by Mitsubishi
is processed with 0.8um triple-poly single-metal CMOS process and
its poly-Si load cell size is 8.0x5.5um**2. 1Mb SRAM by Toshiba
is processed with 0.8um double-poly double-metal CMOS and its poly-Si
load cell size is 5.6x9.5um**2.
Hitachi presents 1Mb SRAM
with 15ns access time. It is processed with 0.8um double-poly double-metal
CMOS process and poly-Si load cell size is 5.2x8.5um**2. 1Mb SRAM
by Fujitsu has an access time of 18ns and is processed with 0.7um
CMOS triple-poly double-metal process. Its poly-Si load cell size
is 4.8x8.5um**2. 1Mb 5V full CMOS SRAM with cell size of 5x12um**2
is presented by Philips. It has an access time of 25ns and is processed
with single poly double-metal 0.7um process. 256Kb BiCMOS SRAM 8ns
1.0um poly-Si load cell 57.4**2, 256K BiCMOS SRAM 12ns National
Semi double poly double metal poly-Si load cell 6.7x14.4.
Hitachi showcases 1Mb
5V SRAM with access time of 9ns built on triple-poly double-metal
0.5um CMOS process. SRAM cell uses poly-Si PMOS load (first in industry)
and has a size of 3.5x6um**2.
Four Japanese companies
debut their 4Mb SRAM. Two of those use poly-Si load cell and the
other two use poly-Si PMOS load cell. NEC presents 5V SRAM with
15ns access time built on 0.55um CMOS triple-poly and double-metal
process. The poly-Si resistor load cell has a size of 3.4x5.6um**2.
3.3V 4Mb SRAM by Toshiba is processed with 0.5um CMOS triple-poly
double-metal process. Its cell uses poly-Si PMOS as a load and has
a size of 3.5x5.8um**2. 4Mb 5V 23ns SRAM by Hitachi is built on
0.5um CMOS 4-poly double-metal process and the size of poly-Si PMOS
load cell is 3.2x5.3um**2. 3.3V 4Mb SRAM with 20ns access time by
Mitsubishi is processed with 0.6um CMOS 4-poly double-metal process
and its poly-Si resistor cell has a size of 3.5x5.3um**2.
TFT PMOS load becomes
the standard feature for SRAM density starting at 4Mb. As a follow
up to its poly-Si load 4Mb SRAM presented a year earlier, Mitsubishi
presents 3V 4Mb SRAM processed with 4-poly double-metal 0.6um CMOS
process using TFT PMOS as a load with a cell size of 3.69x5.3um**2.
SRAM enters 16Mb era.
Fujitsu presents 16Mb 15ns 3.3V SRAM using 0.4um CMOS 4-poly double-metal
process with PMOS TFT load cell with size of 2.1x4.15um**2. 3.3V
16Mb SRAM by NEC has an access time of 12ns and is also processed
with 0.4um CMOS 4-poly double-metal process with PMOS TFT load cell
with size of 2x4um**2.
Sony presents 3.3V 16Mb
SRAM with 9ns access time built on 0.35um CMOS 4-poly double-metal
process with TFT load cell with size of 2.34x3.55um**2. Hitachi
introduces 2.5V 16Mb SRAM processed with 0.25um CMOS 4-poly triple-metal
process with TFT load cell with a cell size of 1.15x2um**2.
16Mb 3.3V BiCMOS SRAM
is introduced by NEC using 0.4um 4-poly double metal BiCMOS process.
Its cell size is 2x4.26um**2.
SRAM density hits the
plateau at 16Mb after the first 16Mb SRAM was debuted 3 years earlier.
No SRAM density improvement is reported.
Fast SRAM and special
architecture are the main theme of SRAM presentations. No major
density upgrade is reported.
No progress in SRAM density.
SRAM is now processed
with 0.25um CMOS process, resulting in a smaller die and higher
speed. However, SRAM density presented remains at 4Mb and 16Mb.
Speed improvement, synchronous SRAM and cache RAM design are the
Focus is on SRAM speed,
architecture and cache RAM design, similar to the previous year.
Same trend continues without
Same trend continues.
SRAM becomes more important as an ASIC product.
Only two papers, both
describing Itanium cache RAM design, are all on SRAM. SRAM is fading
out of the main stage.
In a joint seesion with
DRAM, four SRAM papers were presented. These papers addressed DDR3
SRAM design, and circuit design techniques on sensing scheme and
error correction. Process technology used in these papers ranged
from 0.10um to 0.15um CMOS. As has been seen in previous 4 years,
ISSCC is no longer a good source to gauge SRAM process technology
innovation and density improvement. Logic technology is where SRAM
technology innovation takes place, where SRAM cell size is one of
the important figure of merits for the technology.